Processing math: 0%

Olaoluwa Adigun - IEEE Xplore Author Profile

Scheduled Maintenance on Monday 1/13/2025

Single article sales and account management will be unavailable from 5:00 AM - 7:00 PM ET (09:00 - 23:00 UTC). We apologize for the inconvenience.

IEEE.org
IEEE Xplore
IEEE SA
IEEE Spectrum
More Sites

- Donate
- Personal Sign In

Institutional Sign In

Institutional Sign In

ADVANCED SEARCH

Author details

Olaoluwa Adigun

Publications

13

Citations

52

Publications by Year

20172024

Co-Authors:

Ranveer ChandraBart KoskoPeder A. Olsen

Olaoluwa Adigun

Affiliation

Department of Electrical and Computer Engineering

Signal and Image Processing Institute

Los Angeles, California

Publication Topics

Backward Pass,
Neural Classifier,
Synaptic Weights,
Color Images,
Deep Network,
Forward Pass,
Hidden Layer,
Neural Network,
Active Output,
CIFAR-100 Dataset,
Convolutional Layers,
Cross-entropy

Biography

Olaoluwa (Oliver) Adigun received the Bachelor of Science degree in electronic and electrical engineering from Obafemi Awolowo University, Ife, Nigeria. He is currently pursuing the Ph.D. degree with the Department of Electrical and Computer Engineering, Signal and Image Processing Institute, University of Southern California, Los Angeles, CA, USA.,He has been an Intern with Google AI, Mountain View, CA, USA, and with the Machine Learning Group, Amazon, Seattle, WA, USA.,Mr. Adigun shared the Best Paper Award for his research on noise-boosted recurrent backpropagation at the 2017 International Joint Conference on Neural Networks.(Based on document published on 28 June 2019).

Publications

13

Citations

52

Publications by Year

20172024

Co-Authors:

Ranveer Chandra
Bart Kosko
Peder A. Olsen

Author's Published Works

Search History

Showing 1-25 of 94 results

Journals (56)

Conferences (37)

Early Access Articles (1)

Sort

Filter Results

Show

Open Access Only

Range
Single Year
Sanghun Jeon(78)
Giuk Kim(20)
Sangho Lee(17)
Hunbeom Shin(17)
Junghyeon Hwang(13)
School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea(21)
School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea(16)
School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Korea(5)
Department of Applied Physics, Korea University, Sejong, South Korea(4)
School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea(4)
IEEE Electron Device Letters(25)
IEEE Transactions on Electron Devices(22)
2024 IEEE International Electron Devices Meeting (IEDM)(3)
IEEE Journal of the Electron Devices Society(3)
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.(2)
IEEE(94)
San Francisco, CA, USA(10)
Honolulu, HI, USA(5)
Kyoto, Japan(3)
Glasgow, UK(2)
HsinChu, Taiwan(2)
Ferroelectric Field-effect Transistor(19)
Rapid Thermal Annealing(19)
Ferroelectric Layer(18)
Ferroelectric Materials(15)
Gate Dielectric(15)

Select All on Page

Sort By

Results

Imprinted Antiferroelectric with Low Damage Process for High Performance Negative Capacitance NAND Flash Memory

Sangho Lee;Giuk Kim;Yunseok Nam;Yeongseok Jeong;Taeho Kim;Hunbeom Shin;Sangmok Lee;Jinho Ahn;Sanghun Jeon

IEEE Electron Device Letters

Year: 2025 | Early Access Article |

The concept of negative capacitance (NC), originating from the intrinsic energy configuration of HZO ferroelectrics, has been predominantly utilized in logic transistors to achieve a steeper Id-Vg characteristic. Departing from these conventional approaches, we have developed an NC-NAND flash memory by integrating the NC phenomenon into the blocking oxide layer of conventional NAND flash memory. B...Show More

Imprinted Antiferroelectric with Low Damage Process for High Performance Negative Capacitance NAND Flash Memory

Sangho Lee;Giuk Kim;Yunseok Nam;Yeongseok Jeong;Taeho Kim;Hunbeom Shin;Sangmok Lee;Jinho Ahn;Sanghun Jeon

IEEE Electron Device Letters

Year: 2025 | Early Access Article |

Oxide Channel Ferroelectric NAND Device with Source-Tied Covering Metal Structure: Wide Memory Window (14.3 V), Reliable Retention (> 10 Years) and Disturbance Immunity $(\Delta \mathrm{V}_{\text{th}}\leq 0.1\mathrm{V})$ for QLC Operation

Hongrae Joh;Giuk Kim;Jihye Ock;Seungyeob Kim;Sangmok Lee;Sangho Lee;Kwangsoo Kim;Suhwan Lim;Jongho Woo;Wanki Kim;Daewon Ha;Jinho Ahn;Sanghun Jeon

2024 IEEE International Electron Devices Meeting (IEDM)

Year: 2024 | Conference Paper |

HTML

We show an oxide-channel (Ox. Ch.) based gate-injection type ferroelectric NAND (FeNAND) device with source-tied covering metal (SCM) and control dielectric (C.DE). The SCM and C.DE play crucial roles in the performance enhancement of FeNAND cells. (i) The proposed structure addresses the channel depletion issue of Ox.Ch. by utilizing accumulated holes in the grounded SCM during ERS. This increase...Show More

Oxide Channel Ferroelectric NAND Device with Source-Tied Covering Metal Structure: Wide Memory Window (14.3 V), Reliable Retention (> 10 Years) and Disturbance Immunity $(\Delta \mathrm{V}_{\text{th}}\leq 0.1\mathrm{V})$ for QLC Operation

Hongrae Joh;Giuk Kim;Jihye Ock;Seungyeob Kim;Sangmok Lee;Sangho Lee;Kwangsoo Kim;Suhwan Lim;Jongho Woo;Wanki Kim;Daewon Ha;Jinho Ahn;Sanghun Jeon

2024 IEEE International Electron Devices Meeting (IEDM)

Year: 2024 | Conference Paper |

Design Methodology for Low-Voltage Operational (≤1 V) FRAM Cell Capacitors and Approaches for Overcoming Disturb Issues in 1T-nC Arrays: Experimental & Modeling

Sangho Lee;Giuk Kim;Chaeheon Kim;Yangjin Jung;Jeonghyun Hwang;Yunseok Nam;Mincheol Shin;Youngin Goh;Mintae Ryu;Jihye Suh;Kilho Lee;Wanki Kim;Daewon Ha;Jinho Ahn;Sanghun Jeon

2024 IEEE International Electron Devices Meeting (IEDM)

Year: 2024 | Conference Paper |

HTML

In this work, we provide a methodology for designing an anti-ferroelectric(AFE) based FRAM cell capacitor that operates at low voltage $(\leq$ 1 V), while achieving superior high and steep polarization $(\Delta \mathrm{P})$ switching characteristics (23.5 µC/cm2), considering BEOL compatibility (process temp. $\leq$ 400 °C). Furthermore, through experimental demonstration and modeling, we validate...Show More

Design Methodology for Low-Voltage Operational (≤1 V) FRAM Cell Capacitors and Approaches for Overcoming Disturb Issues in 1T-nC Arrays: Experimental & Modeling

Sangho Lee;Giuk Kim;Chaeheon Kim;Yangjin Jung;Jeonghyun Hwang;Yunseok Nam;Mincheol Shin;Youngin Goh;Mintae Ryu;Jihye Suh;Kilho Lee;Wanki Kim;Daewon Ha;Jinho Ahn;Sanghun Jeon

2024 IEEE International Electron Devices Meeting (IEDM)

Year: 2024 | Conference Paper |

Unveiling the Origin of Disturbance in FeFET and the Potential of Multifunctional TiO2 as a Breakthrough for Disturb-Free 3D NAND Cell: Experimental and Modeling

Giuk Kim;Hyunjun Kang;Sangho Lee;Hyojun Choi;Yangjin Jung;Mincheol Shin;Kwangsoo Kim;Suhwan Lim;Jongho Woo;Wanki Kim;Daewon Ha;Jinho Ahn;Sanghun Jeon

2024 IEEE International Electron Devices Meeting (IEDM)

Year: 2024 | Conference Paper |

HTML

We reveal the origin of disturbance issues in ferroelectric FETs (FeFETs) with a metal-gate interlayer (G.IL)-ferroelectric (FE)-channel interlayer (Ch.IL)-Si (MIFIS) stack. To achieve both low-voltage operation and disturbance immunity, we introduce a multi-functional $\text{TiO}_{2}$ layer, positioned between the G.IL and FE layer. $\text{TiO}_{2}$ multi-functional layer (MFL) serves two pivotal...Show More

Unveiling the Origin of Disturbance in FeFET and the Potential of Multifunctional TiO2 as a Breakthrough for Disturb-Free 3D NAND Cell: Experimental and Modeling

Giuk Kim;Hyunjun Kang;Sangho Lee;Hyojun Choi;Yangjin Jung;Mincheol Shin;Kwangsoo Kim;Suhwan Lim;Jongho Woo;Wanki Kim;Daewon Ha;Jinho Ahn;Sanghun Jeon

2024 IEEE International Electron Devices Meeting (IEDM)

Year: 2024 | Conference Paper |

Optimizing De-Trap Pulses in Gate-Injection Type Ferroelectric NAND Cells to Minimize Read After Write Delay Issue

Giuk Kim;Hyojun Choi;Hongrae Cho;Sangho Lee;Hunbeom Shin;Hyunjun Kang;Hoon Kim;Seokjoong Shin;Seonjae Park;Sunseong Kwon;Youngjin Lim;Kang Kim;Jong Min Chung;Il-Kwon Oh;Sang-Hee Ko Park;Jinho Ahn;Sanghun Jeon

IEEE Electron Device Letters

Year: 2024 | Volume: 45, Issue: 12 | Journal Article |

HTML

The ferroelectric (FE) NAND flash, featuring metal-interlayer-FE-interlayer-silicon (MIFIS) gate stacks, leverages both charge trapping and polarization (P) switching to achieve a broad memory window (MW) and low operation voltage. These remarkable advancements establish it as a viable contender for future NAND flash technologies. However, the read-after-write-delay (RAWD) problem during program/e...Show More

Optimizing De-Trap Pulses in Gate-Injection Type Ferroelectric NAND Cells to Minimize Read After Write Delay Issue

Giuk Kim;Hyojun Choi;Hongrae Cho;Sangho Lee;Hunbeom Shin;Hyunjun Kang;Hoon Kim;Seokjoong Shin;Seonjae Park;Sunseong Kwon;Youngjin Lim;Kang Kim;Jong Min Chung;Il-Kwon Oh;Sang-Hee Ko Park;Jinho Ahn;Sanghun Jeon

IEEE Electron Device Letters

Year: 2024 | Volume: 45, Issue: 12 | Journal Article |

The Effect of Ferroelectric/Dielectric Capacitance Ratio on Short-Term Retention Characteristics of MFMIS FeFET

Junghyeon Hwang;Giuk Kim;Hongrae Joh;Jinho Ahn;Sanghun Jeon

IEEE Journal of the Electron Devices Society

Year: 2024 | Volume: 12 | Journal Article |

HTML

Metal-ferroelectric-metal-insulator-semiconductor (MFMIS) FeFETs have significant potential for use in non-volatile memory applications. This is primarily due to their compatibility with CMOS technology and reliable switching characteristics. Previous studies have primarily concentrated on the endurance and memory window properties, while this study focuses on the short-term (< $1~\mu $ s) retenti...Show More

The Effect of Ferroelectric/Dielectric Capacitance Ratio on Short-Term Retention Characteristics of MFMIS FeFET

Junghyeon Hwang;Giuk Kim;Hongrae Joh;Jinho Ahn;Sanghun Jeon

IEEE Journal of the Electron Devices Society

Year: 2024 | Volume: 12 | Journal Article |

Kinetically Stabilized Hafnia Ferroelectric of Al-Doped HfO₂ Film by Fast Ramping and Fast Cooling Process

Lingwei Zhang;Giuk Kim;Sangho Lee;Hunbeom Shin;Youngjin Lim;Kang Kim;Il-Kwon Oh;Sang-Hee Ko Park;Jinho Ahn;Sanghun Jeon

IEEE Transactions on Electron Devices

Year: 2024 | Volume: 71, Issue: 12 | Journal Article |

HTML

Hafnia-based ferroelectrics (FEs) can be stabilized via careful engineering, both kinetically and thermodynamically. Especially, the fast cooling process has been regarded as an efficient approach for kinetically maximizing the phase transition to the orthorhombic (o-) phase from the tetragonal (t-) phase, which stabilizes thermodynamically during crystallization annealing. However, accurately con...Show More

Kinetically Stabilized Hafnia Ferroelectric of Al-Doped HfO₂ Film by Fast Ramping and Fast Cooling Process

Lingwei Zhang;Giuk Kim;Sangho Lee;Hunbeom Shin;Youngjin Lim;Kang Kim;Il-Kwon Oh;Sang-Hee Ko Park;Jinho Ahn;Sanghun Jeon

IEEE Transactions on Electron Devices

Year: 2024 | Volume: 71, Issue: 12 | Journal Article |

Experimental Analysis on the Interaction Between Interface Trap Charges and Polarization on the Memory Window of Metal-Ferroelectric–Insulator-Si (MFIS) FeFET

Giuk Kim;Hyojun Choi;Sangho Lee;Hunbeom Shin;Sangmok Lee;Yunseok Nam;Hyunjun Kang;Seokjoong Shin;Hoon Kim;Youngjin Lim;Kang Kim;Il-Kwon Oh;Sang-Hee Ko Park;Jinho Ahn;Sanghun Jeon

IEEE Transactions on Electron Devices

Year: 2024 | Volume: 71, Issue: 11 | Journal Article |

HTML

In this study, we investigated the impact of unstable and stable interface trap charges ( ${Q}_{\text {it}}\text {)}$ on ${P}_{\text {S}}$ switching in metal-ferroelectric–insulator-Si (MFIS) ferroelectric field-effect transistors (FeFETs), which vary with the thickness of the insulator. We also examine how these variations ultimately affect the various performance metrics of MFIS FeFETs. To ac...Show More

Experimental Analysis on the Interaction Between Interface Trap Charges and Polarization on the Memory Window of Metal-Ferroelectric–Insulator-Si (MFIS) FeFET

Giuk Kim;Hyojun Choi;Sangho Lee;Hunbeom Shin;Sangmok Lee;Yunseok Nam;Hyunjun Kang;Seokjoong Shin;Hoon Kim;Youngjin Lim;Kang Kim;Il-Kwon Oh;Sang-Hee Ko Park;Jinho Ahn;Sanghun Jeon

IEEE Transactions on Electron Devices

Year: 2024 | Volume: 71, Issue: 11 | Journal Article |

Positive Interaction Between Charge Trapping and Polarization Switching in Metal-Interlayer-Ferroelectric-Interlayer-Silicon (MIFIS) Ferroelectric Field-Effect Transistor

Hyojun Choi;Giuk Kim;Sangho Lee;Hunbeom Shin;Youngjin Lim;Kang Kim;Do-Hyung Kim;Il-Kwon Oh;Sang-Hee Ko Park;Jinho Ahn;Sanghun Jeon

IEEE Electron Device Letters

Year: 2024 | Volume: 45, Issue: 12 | Journal Article |

HTML

This study employs analytical simulation to illustrate the beneficial correlation between interface trapped charge and spontaneous polarization ( ${P}_{\text {S}}$ ) switching behavior in the MIFIS gate stack. We found that there is a positive interaction between charge trapping and polarization switching, comprising three sequential processes. 1) In the process of program (erase) operation, elect...Show More

Positive Interaction Between Charge Trapping and Polarization Switching in Metal-Interlayer-Ferroelectric-Interlayer-Silicon (MIFIS) Ferroelectric Field-Effect Transistor

Hyojun Choi;Giuk Kim;Sangho Lee;Hunbeom Shin;Youngjin Lim;Kang Kim;Do-Hyung Kim;Il-Kwon Oh;Sang-Hee Ko Park;Jinho Ahn;Sanghun Jeon

IEEE Electron Device Letters

Year: 2024 | Volume: 45, Issue: 12 | Journal Article |

In-depth Analysis of the Hafnia Ferroelectrics as a Key Enabler for Low Voltage & QLC 3D VNAND Beyond 1K Layers: Experimental Demonstration and Modeling

Giuk Kim;Hyojun Choi;Hunbeom Shin;Sangho Lee;Sangmok Lee;Yunseok Nam;Minhyun Jung;Ilho Myeong;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Wanki Kim;Daewon Ha;Jinho Ahn;Sanghun Jeon

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Year: 2024 | Conference Paper |

Cited by: Papers (2)

HTML

In this work, we experimentally demonstrate a remarkable performance improvement, boosted by the interaction of charge trapping & ferroelectric (FE) switching effects in metal-band engineered gate interlayer (BE-G.IL)- FE-channel interlayer (Ch.IL)-Si (MIFIS) FeFET. The MIFIS with BE-G.IL (BE-MIFIS) facilitates the maximized ‘positive feedback’ (Posi. FB.) of dual effects, leading to low operation...Show More

In-depth Analysis of the Hafnia Ferroelectrics as a Key Enabler for Low Voltage & QLC 3D VNAND Beyond 1K Layers: Experimental Demonstration and Modeling

Giuk Kim;Hyojun Choi;Hunbeom Shin;Sangho Lee;Sangmok Lee;Yunseok Nam;Minhyun Jung;Ilho Myeong;Kijoon Kim;Jongho Woo;Suhwan Lim;Kwangsoo Kim;Wanki Kim;Daewon Ha;Jinho Ahn;Sanghun Jeon

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Year: 2024 | Conference Paper |

Low-Damage Processed and High-Pressure Annealed High-k Hafnium Zirconium Oxide Capacitors near Morphotropic Phase Boundary with Record-Low EOT of 2.4Å & high-k of 70 for DRAM Technology

Venkateswarlu Gaddam;Junghyeon Hwang;Hunbeom Shin;Chaeheon Kim;Giuk Kim;Hyung-Jun Kim;Jooho Lee;Hyun-Cheol Kim;Bumsu Park;Suhwan Lim;Sang Yun Kim;Kwangsoo Kim;Sungho Lee;Daewon Ha;Jinho Ahn;Sanghun Jeon

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Year: 2024 | Conference Paper |

HTML

We present record-low equivalent oxide thickness (EOT) of 2.4 Å with a remarkable dielectric constant (K) of 64 at 4.1nm-thick hafnium-based films with no wake-up characteristics. In comparison to conventional HZO films, our remarkable achievement stems from the high-quality crystalline structure with less oxygen vacancies formed by a low-damage process, as evidenced by high-angle annular dark-fie...Show More

Low-Damage Processed and High-Pressure Annealed High-k Hafnium Zirconium Oxide Capacitors near Morphotropic Phase Boundary with Record-Low EOT of 2.4Å & high-k of 70 for DRAM Technology

Venkateswarlu Gaddam;Junghyeon Hwang;Hunbeom Shin;Chaeheon Kim;Giuk Kim;Hyung-Jun Kim;Jooho Lee;Hyun-Cheol Kim;Bumsu Park;Suhwan Lim;Sang Yun Kim;Kwangsoo Kim;Sungho Lee;Daewon Ha;Jinho Ahn;Sanghun Jeon

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Year: 2024 | Conference Paper |

HZO (>10 nm) Films for Achieving High-κ Near Morphotropic Phase Boundary at Low-Temperature Furnace Annealing Process

Yixin Qin;Venkateswarlu Gaddam;Taeseung Jung;Sanghun Jeon

IEEE Transactions on Electron Devices

Year: 2024 | Volume: 71, Issue: 9 | Journal Article |

HTML

Recently, hafnium zirconium oxide ( ${\mathrm {Hf}}_{x}{\mathrm {Zr}}_{{{1}}-{x}}{\mathrm {O}}_{2}$ , HZO) films gained considerable attention in sensors, displays, and memory devices. However, one of the main drawbacks of HZO material is that as the film thickness increases, the dielectric constant ( $\kappa$ ) can deteriorate. To address this issue, we investigated a study on the enhancement of ...Show More

HZO (>10 nm) Films for Achieving High-κ Near Morphotropic Phase Boundary at Low-Temperature Furnace Annealing Process

Yixin Qin;Venkateswarlu Gaddam;Taeseung Jung;Sanghun Jeon

IEEE Transactions on Electron Devices

Year: 2024 | Volume: 71, Issue: 9 | Journal Article |

First Demonstration of Thermally Stable Zr:HfO2 Ferroelectrics via Inserting AlN Interlayer

Sangmok Lee;Giuk Kim;Sangho Lee;Hunbeom Shin;Youngjin Lim;Kang Kim;Do-Hyung Kim;Il-Kwon Oh;Sang-Hee Ko Park;Jinho Ahn;Sanghun Jeon

IEEE Electron Device Letters

Year: 2024 | Volume: 45, Issue: 9 | Journal Article |

HTML

This letter introduces a novel methodology to improve the thermal stability of Zr:HfO2 (HZO) ferroelectric (FE) materials by adding AlN as the middle interlayer (IL) between HZO. Adding AlN to HZO improves the thermal stability of FE layers in three ways. Initially, the growth of grains and the formation of the dielectric monoclinic (m-) phase are kinetically suppressed in the HZO when subjected t...Show More

First Demonstration of Thermally Stable Zr:HfO2 Ferroelectrics via Inserting AlN Interlayer

Sangmok Lee;Giuk Kim;Sangho Lee;Hunbeom Shin;Youngjin Lim;Kang Kim;Do-Hyung Kim;Il-Kwon Oh;Sang-Hee Ko Park;Jinho Ahn;Sanghun Jeon

IEEE Electron Device Letters

Year: 2024 | Volume: 45, Issue: 9 | Journal Article |

Novel Strategies Toward High-Performance FeFET for Computing In Memory Application

Giuk Kim;Hyojun Choi;Sangho Lee;Hunbeom Shin;Lingwei Zhang;Sangmok Lee;Yunseok Nam;Woongjin Kim;Jihye Ock;Sujeong Lee;Hyunjun Kang;Sanghun Jeon

2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)

Year: 2024 | Conference Paper |

Cited by: Papers (2)

HTML

Ferroelectric Field-Effect Transistors (FeFETs) attract the interest of researchers due to their capability of low power and high-speed operation for computing in memory (CIM). However, challenges with the poor memory window (MW) and reliability of FeFETs have triggered problems of density and reliability for CIM. Our study addresses these obstacles through a comprehensive approach, including mate...Show More

Novel Strategies Toward High-Performance FeFET for Computing In Memory Application

Giuk Kim;Hyojun Choi;Sangho Lee;Hunbeom Shin;Lingwei Zhang;Sangmok Lee;Yunseok Nam;Woongjin Kim;Jihye Ock;Sujeong Lee;Hyunjun Kang;Sanghun Jeon

2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)

Year: 2024 | Conference Paper |

Charge Trap Flash with Superior Program Efficiency by Negative Capacitance-Boosting Effect

Giuk Kim;Hyojun Choi;Sangho Lee;Hunbeom Shin;Lingwei Zhang;Sangmok Lee;Yunseok Nam;Woongjin Kim;Jihye Ock;Sujeong Lee;Hyunjun Kang;Sanghun Jeon

2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)

Year: 2024 | Conference Paper |

HTML

The 3D NAND flash architecture has adopted the incremental step pulse program (ISPP) operation, involving the repetition of program (PGM) & read, with the aim of reducing the Vth variation. However, the repetitive PGM & read operations degrade the memory window (MW) and endurance properties of the charge trap flash (CTF) device. Thus, enhancements for MW and fast PGM speed are consistently desired...Show More

Charge Trap Flash with Superior Program Efficiency by Negative Capacitance-Boosting Effect

Giuk Kim;Hyojun Choi;Sangho Lee;Hunbeom Shin;Lingwei Zhang;Sangmok Lee;Yunseok Nam;Woongjin Kim;Jihye Ock;Sujeong Lee;Hyunjun Kang;Sanghun Jeon

2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)

Year: 2024 | Conference Paper |

Design of Physically Unclonable Function Using Ferroelectric FET With Auto Write-Back Technique for Resource-Limited IoT Security

Sehee Lim;Junghyeon Hwang;Dong Han Ko;Se Keon Kim;Tae Woo Oh;Sanghun Jeon;Seong-Ook Jung

IEEE Internet of Things Journal

Year: 2024 | Volume: 11, Issue: 16 | Journal Article |

HTML

Physically unclonable function (PUF) is a lightweight encryption technique that generates random digital keys (responses) using intrinsic process variations of devices, which is a promising solution for Internet of Things (IoT) security due to its compatibility with constrained resources. Recent attempts to adopt nonvolatile memory (NVM) into PUFs have enhanced stability through a write-back techn...Show More

Design of Physically Unclonable Function Using Ferroelectric FET With Auto Write-Back Technique for Resource-Limited IoT Security

Sehee Lim;Junghyeon Hwang;Dong Han Ko;Se Keon Kim;Tae Woo Oh;Sanghun Jeon;Seong-Ook Jung

IEEE Internet of Things Journal

Year: 2024 | Volume: 11, Issue: 16 | Journal Article |

Ultrafast (50 ns) ID–VG Analysis on Oxide Thin-Film Transistors With Morphotropic Phase Boundary State High-κ Gate Insulator

Taeseung Jung;Sooji Nam;Sanghun Jeon

IEEE Transactions on Electron Devices

Year: 2024 | Volume: 71, Issue: 5 | Journal Article |

HTML

The advancement of oxide thin-film transistors (TFTs) with high-performance is crucial for high-resolution, high-framerate displays as they serve as switching and driving elements. To ensure high mobility characteristics and withstand relatively high supply voltage (5 V), a TFT panel must have a high- $\kappa $ gate dielectric (DE) with comparatively thick thickness and good interfacial quality. ...Show More

Ultrafast (50 ns) ID–VG Analysis on Oxide Thin-Film Transistors With Morphotropic Phase Boundary State High-κ Gate Insulator

Taeseung Jung;Sooji Nam;Sanghun Jeon

IEEE Transactions on Electron Devices

Year: 2024 | Volume: 71, Issue: 5 | Journal Article |

Design Guidelines of Hafnia Ferroelectrics and Gate-Stack for Multilevel-Cell FeFET

Sangho Lee;Giuk Kim;Youngkyu Lee;Hunbeom Shin;Youngseok Jeong;Lingwei Zhang;Seong-Ook Jung;Sanghun Jeon

IEEE Transactions on Electron Devices

Year: 2024 | Volume: 71, Issue: 3 | Journal Article |

Cited by: Papers (3)

HTML

In this work, we demonstrate a novel approach to superior multilevel-cell (MLC) ferroelectric field-effect transistor (FeFET) with a large memory window (MW) and negligible ${V}_{T}$ variation toward MLC operation. We realized high ferroelectricity in a relatively thick HZO ferroelectric (FE) layer for FeFET with a large MW [MW $\propto $ thickness of FE layer ( ${T}_{\text {FE}}$ )] based on ...Show More

Design Guidelines of Hafnia Ferroelectrics and Gate-Stack for Multilevel-Cell FeFET

Sangho Lee;Giuk Kim;Youngkyu Lee;Hunbeom Shin;Youngseok Jeong;Lingwei Zhang;Seong-Ook Jung;Sanghun Jeon

IEEE Transactions on Electron Devices

Year: 2024 | Volume: 71, Issue: 3 | Journal Article |

Ultra-high Tunneling Electroresistance Ratio (2 × 104) & Endurance (108) in Oxide Semiconductor-Hafnia Self-rectifying (1.5 × 103) Ferroelectric Tunnel Junction

Junghyeon Hwang;Chaeheon Kim;Hunbeom Shin;Hwayoung Kim;Sang-Hee Ko Park;Sanghun Jeon

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Year: 2023 | Conference Paper |

Cited by: Papers (1)

HTML

In this study, we present a remarkable improvement in the performance of hafnia-based ferroelectric tunnel junctions (FTJs) using oxygen scavenging technology and extremely low-damage (ELD) deposition, leading to a significant increase in the tunneling electroresistance ratio $({\mathrm {TER}}) (\gt 2 \times 10^{4})$, on-current density $(\gt 10^{-2}\mathrm{A} /cm^{2})$, and self-rectifying ratio ...Show More

Ultra-high Tunneling Electroresistance Ratio (2 × 104) & Endurance (108) in Oxide Semiconductor-Hafnia Self-rectifying (1.5 × 103) Ferroelectric Tunnel Junction

Junghyeon Hwang;Chaeheon Kim;Hunbeom Shin;Hwayoung Kim;Sang-Hee Ko Park;Sanghun Jeon

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Year: 2023 | Conference Paper |

Development of MFMIS Gatestack with Thick Hafnium Zirconium Oxide (HZO) for Nonvolatile Memory Application

Bohyeon Kang;Jongseo Park;Junghyeon Hwang;Sangho Lee;Hunbeom Shin;Jehyun An;Hyunseo You;Sung-Min Ahn;Sanghun Jeon;Rock-Hyun Baek

2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)

Year: 2023 | Conference Paper |

HTML

In this work, a thick HZO-based gate device is examined for memory applications owing to its wider memory window. The TiN - HZO- TiN film layers are demonstrated by measuring electrical properties such as polarization, capacitance, and current. In addition, to apply a thick HZO stack to an integrated memory device, we develop an MFMIS etching process and define a gate structure with a sufficient m...Show More

Development of MFMIS Gatestack with Thick Hafnium Zirconium Oxide (HZO) for Nonvolatile Memory Application

Bohyeon Kang;Jongseo Park;Junghyeon Hwang;Sangho Lee;Hunbeom Shin;Jehyun An;Hyunseo You;Sung-Min Ahn;Sanghun Jeon;Rock-Hyun Baek

2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)

Year: 2023 | Conference Paper |

Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices

Sehee Lim;Youngin Goh;Young Kyu Lee;Dong Han Ko;Junghyeon Hwang;Yeongseok Jeong;Hunbeom Shin;Sanghun Jeon;Seong-Ook Jung

IEEE Journal of Solid-State Circuits

Year: 2023 | Volume: 58, Issue: 7 | Journal Article |

Cited by: Papers (9)

HTML

This study proposes a self-rectifying ferroelectric tunnel junction (SR-FTJ) crosspoint array to satisfy the stringent size requirements of the Internet-of-Things devices. Each cell in the SR-FTJ crosspoint array consists of two SR-FTJs stacked vertically, resulting in ultrahigh density. The SR-FTJ crosspoint array can operate as: 1) ternary content-addressable memory (TCAM) or 2) binary content a...Show More

Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices

Sehee Lim;Youngin Goh;Young Kyu Lee;Dong Han Ko;Junghyeon Hwang;Yeongseok Jeong;Hunbeom Shin;Sanghun Jeon;Seong-Ook Jung

IEEE Journal of Solid-State Circuits

Year: 2023 | Volume: 58, Issue: 7 | Journal Article |

Effect of Floating Gate Insertion on the Analog States of Ferroelectric Field-Effect Transistors

Sangho Lee;Youngkyu Lee;Giuk Kim;Taeho Kim;Taehyong Eom;Seong-Ook Jung;Sanghun Jeon

IEEE Transactions on Electron Devices

Year: 2023 | Volume: 70, Issue: 1 | Journal Article |

Cited by: Papers (10)

HTML

In this work, we propose a structural approach to mitigate device-to-device variation and performance degradation of ferroelectric (FE) field-effect transistors (FeFETs) due to the inhomogeneity of FE and dielectric (DE) phases of the FE layer. We found that by inserting a floating gate below the FE layer, the polarization effect of FE grains is equalized, thus suppressing the formation of an unde...Show More

Effect of Floating Gate Insertion on the Analog States of Ferroelectric Field-Effect Transistors

Sangho Lee;Youngkyu Lee;Giuk Kim;Taeho Kim;Taehyong Eom;Seong-Ook Jung;Sanghun Jeon

IEEE Transactions on Electron Devices

Year: 2023 | Volume: 70, Issue: 1 | Journal Article |

Oxygen Vacancy Control as a Strategy to Enhance Imprinting Effect in Hafnia Ferroelectric Devices

Yeongseok Jeong;Venkateswarlu Gaddam;Youngin Goh;Hunbeom Shin;Sangho Lee;Giuk Kim;Sanghun Jeon

IEEE Transactions on Electron Devices

Year: 2023 | Volume: 70, Issue: 1 | Journal Article |

Cited by: Papers (8)

HTML

Hafnia-based ferroelectric materials are recently drawing a significant attention for future electronic devices; however, there is a need to further enhance their functionality for practical applications. Especially, an imprinting effect has been regarded as a defect to be reduced in ferroelectrics; yet, it can be positively applied to various electronic devices with the functionality of self-rect...Show More

Oxygen Vacancy Control as a Strategy to Enhance Imprinting Effect in Hafnia Ferroelectric Devices

Yeongseok Jeong;Venkateswarlu Gaddam;Youngin Goh;Hunbeom Shin;Sangho Lee;Giuk Kim;Sanghun Jeon

IEEE Transactions on Electron Devices

Year: 2023 | Volume: 70, Issue: 1 | Journal Article |

Triple-Node FinFET With Non-Ohmic Schottky Junctions for Synaptic Devices

Ji-Man Yu;Seong-Yeon Kim;Jin-Ki Kim;Joon-Kyu Han;Seung-Bae Jeon;Yang-Kyu Choi

IEEE Electron Device Letters

Year: 2023 | Volume: 44, Issue: 1 | Journal Article |

Cited by: Papers (3)

HTML

A triple-node FinFET (TriNo-FinFET) with non-ohmic Schottky junctions is demonstrated for an artificial synapse. The three mechanisms of thermionic emission in a subthreshold region, tunneling in a transition region, and drift transport in an inversion region are utilized in the TriNo-FinFET with non-ohmic Schottky junctions. The transition region dominated by tunneling with non-ohmic Schottky jun...Show More

Triple-Node FinFET With Non-Ohmic Schottky Junctions for Synaptic Devices

Ji-Man Yu;Seong-Yeon Kim;Jin-Ki Kim;Joon-Kyu Han;Seung-Bae Jeon;Yang-Kyu Choi

IEEE Electron Device Letters

Year: 2023 | Volume: 44, Issue: 1 | Journal Article |

Design Guidelines of Thermally Stable Hafnia Ferroelectrics for the Fabrication of 3D Memory Devices

Giuk Kim;Hunbeom Shin;Taehyong Eom;Minhyun Jung;Taeho Kim;Sangho Lee;Minki Kim;Yeongseok Jeong;Ji-Sung Kim;Kab-Jin Nam;Bong Jin Kuh;Sanghun Jeon

2022 International Electron Devices Meeting (IEDM)

Year: 2022 | Conference Paper |

Cited by: Papers (6)

HTML

We provide a methodology for designing thermally stable hafnia ferroelectric (FE) materials to be taken into account while fabricating 3D memory devices. We reveal the underlying origins for the thermal instability of hafnia FE materials in terms of kinetics and material science. Furthermore, we suggest adopting dopants whose ionic radius is smaller than Hf in the FE matrix as a feasible option to...Show More

Design Guidelines of Thermally Stable Hafnia Ferroelectrics for the Fabrication of 3D Memory Devices

Giuk Kim;Hunbeom Shin;Taehyong Eom;Minhyun Jung;Taeho Kim;Sangho Lee;Minki Kim;Yeongseok Jeong;Ji-Sung Kim;Kab-Jin Nam;Bong Jin Kuh;Sanghun Jeon

2022 International Electron Devices Meeting (IEDM)

Year: 2022 | Conference Paper |

IEEE Personal Account

Change username/password

Purchase Details

Payment Options
View Purchased Documents

Profile Information

Communications Preferences
Profession and Education
Technical interests

Need Help?

US & Canada: +1 800 678 4333
Worldwide: +1 732 981 0060
Contact & Support

Follow

About IEEE Xplore | Contact Us | Help | Accessibility | Terms of Use | Nondiscrimination Policy | IEEE Ethics Reporting | Sitemap | IEEE Privacy Policy

A public charity, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.

© Copyright 2025 IEEE - All rights reserved, including rights for text and data mining and training of artificial intelligence and similar technologies.

IEEE Account

Change Username/Password
Update Address

Purchase Details

Payment Options
Order History
View Purchased Documents

Profile Information

Communications Preferences
Profession and Education
Technical Interests

Need Help?

US & Canada: +1 800 678 4333
Worldwide: +1 732 981 0060
Contact & Support

About IEEE Xplore
Contact Us
Help
Accessibility
Terms of Use
Nondiscrimination Policy
Sitemap
Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.
© Copyright 2025 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.

Test Whats new message.