Jingxiao Zheng - IEEE Xplore Author Profile

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Author details

Jingxiao Zheng

Publications

10

Citations

279

Publications by Year

20162022

Co-Authors:

Dragomir AnguelovAnkan BansalNavaneeth BodlaCarlos D. CastilloVisesh Chari

Show All Co-Authors (29)

Jingxiao Zheng

Affiliation

Waymo LLC

Publication Topics

Deep Convolutional Neural Network,
Face Recognition,
Still Images,
Challenging Dataset,
Face Detection,
Video Frames,
Video Surveillance,
Bounding Box,
Deep Features,
Descriptive Characteristics,
Face Alignment,
Feature Maps

Biography

Jingxiao Zheng received the B.Eng. degree from Southeast University, Nanjing, in 2012 and the M.S. degree from the University of Maryland at College Park in 2014, where he is currently a Research Assistant with the Institute for Advanced Computer Studies. His advisor is Prof. R. Chellappa. His research interests include deep learning, face recognition, and action recognition.(Based on document published on 2 April 2019).

Publications

10

Citations

279

Publications by Year

20162022

Co-Authors:

Dragomir Anguelov
Ankan Bansal
Navaneeth Bodla
Carlos D. Castillo
Visesh Chari

Show All Co-Authors (29)

Author's Published Works

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Showing 1-25 of 34 results

Conferences (22)

Journals (12)

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T. Nagano(33)
T. Yamanaka(7)
T. Nishida(7)
M. Minami(6)
A. Watanabe(6)
Hitachi Research Laboratory, Hitachi and Limited, Hitachi, Ibaraki, Japan(11)
Central Research Laboratory, Hitachi and Limited, Kokubunji, Tokyo, Japan(6)
Central Research Laboratory, Hitachi and Limited, Tokyo, Japan(5)
Hitachi VLSI Engineering Corporation Limited, Tokyo, Japan(2)
Hitachi Research Laboratory, Hitachi and Limited, Japan(2)
IEEE Transactions on Electron Devices(7)
IEEE Journal of Solid-State Circuits(4)
1986 International Electron Devices Meeting(2)
Digest of Technical Papers., Symposium on VLSI Circuits.(2)
1979 International Electron Devices Meeting(1)
IEEE(34)
Kyoto, Japan(5)
Washington, DC, USA(3)
Honololu, HI, USA(2)
Honolulu, HI, USA(2)
Los Angeles, CA, USA(2)
Gate Length(9)
Gate Electrode(8)
Buried Layer(7)
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A study of analog characteristics of CMOS with heavily nitrided NO oxynitrides

T. Ohguro;T. Nagano;M. Fujiwara;M. Takayanagi;T. Shimizu;H.S. Momose;S. Nakamura;Y. Toyoshima

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

Year: 2001 | Conference Paper |

Cited by: Papers (8) | Patents (4)

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Recently, heavily nitrided NO oxynitride has been proposed as an alternative to pure oxide in order to realize high drivability and suppress a large gate leakage current (Fujiwara et al, Digest of IEDM 2000, pp. 227-30, 2000). However, in general, oxynitride has higher interface state density than that of pure oxide, and brings low frequency noise (or 1/f noise) degradation (Kimijima et al., 1999)...Show More

A study of analog characteristics of CMOS with heavily nitrided NO oxynitrides

T. Ohguro;T. Nagano;M. Fujiwara;M. Takayanagi;T. Shimizu;H.S. Momose;S. Nakamura;Y. Toyoshima

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

Year: 2001 | Conference Paper |

Pseudo-SOI: p-n-p channel-doped bulk MOSFET for low-voltage high-speed applications

M. Miyamoto;R. Nagai;T. Nagano

IEEE Transactions on Electron Devices

Year: 2001 | Volume: 48, Issue: 12 | Journal Article |

Cited by: Papers (2) | Patents (2)

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A pseudo-silicon-on-insulator (P-SOI) MOSFET fabricated using a bulk substrate has been developed for high device performance, comparable to those of a fully depleted (FD) SOI MOSFET, without problems caused by the usage of an SOI substrate. It features a p-n-p channel profile, in which a sandwiched thin n-type layer is fully depleted by the internal built-in potential. The thin n-type layer expan...Show More

Pseudo-SOI: p-n-p channel-doped bulk MOSFET for low-voltage high-speed applications

M. Miyamoto;R. Nagai;T. Nagano

IEEE Transactions on Electron Devices

Year: 2001 | Volume: 48, Issue: 12 | Journal Article |

A 5-inch SVGA low-temperature poly-Si TFT-LCD with integrated digital interface driver

T. Nagano;H. Kageyama;H. Akimoto;Y. Mikami;H. Sato

2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)

Year: 2001 | Conference Paper |

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A high-resolution full-color LCD with integrated digital interface data driver is a strong candidate for mobile Internet appliances. This paper describes a low-temperature poly-Si (LTPS) TFT driver with 5-V/6-bit interface applicable to 5-inch SVGA LCDs. To reduce the driver area overhead, an architecture of multiplexed resistor-string D/A converter followed by synchronized signal distributor with...Show More

A 5-inch SVGA low-temperature poly-Si TFT-LCD with integrated digital interface driver

T. Nagano;H. Kageyama;H. Akimoto;Y. Mikami;H. Sato

2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443)

Year: 2001 | Volume: 2 | Conference Paper |

High performance digital-analog mixed device on an Si substrate with resistivity beyond 1 k/spl Omega/ cm

T. Ohguro;T. Ishikawa;T. Kimura;S. Samata;A. Kawasaki;T. Nagano;T. Yoshitomi;T. Toyoshima

International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)

Year: 2000 | Conference Paper |

Cited by: Papers (9) | Patents (6)

High performance digital-analog mixed devices are fabricated on a high resistivity MCZ Si substrate with low oxygen in order to suppress substrate noise from digital to analog circuits. The low oxygen prevents substrate resistivity reduction due to thermal donor occurring during device fabrication process. Good characteristics of digital, analog and power amplifiers can be realized by optimizing t...Show More

High performance digital-analog mixed device on an Si substrate with resistivity beyond 1 k/spl Omega/ cm

T. Ohguro;T. Ishikawa;T. Kimura;S. Samata;A. Kawasaki;T. Nagano;T. Yoshitomi;T. Toyoshima

International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)

Year: 2000 | Conference Paper |

An asymmetrically doped buried-layer (ADB) structure for low-voltage mixed analog-digital CMOS LSI's

M. Miyamoto;K. Toyota;K. Seki;T. Nagano

IEEE Transactions on Electron Devices

Year: 1999 | Volume: 46, Issue: 8 | Journal Article |

Cited by: Papers (3) | Patents (3)

A new CMOS structure has been developed that is distinguished by its asymmetrically doped buried layer (ADB). This structure makes it possible to achieve high drain output resistance and high transconductance necessary for high-performance analog circuits with a low-voltage power supply. The ADB structure has a high-impurity-concentration "pocket" layer near the channel edge of the buried layer on...Show More

An asymmetrically doped buried-layer (ADB) structure for low-voltage mixed analog-digital CMOS LSI's

M. Miyamoto;K. Toyota;K. Seki;T. Nagano

IEEE Transactions on Electron Devices

Year: 1999 | Volume: 46, Issue: 8 | Journal Article |

Pseudo-SOI: P-N-P-channel-doped bulk MOSFET for low-voltage high-performance applications

M. Miyamoto;R. Nagai;T. Nagano

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)

Year: 1998 | Conference Paper |

Cited by: Papers (3) | Patents (2)

A "pseudo-SOI (P-SOI)" MOSFET using a bulk substrate with small subthreshold swing, high drain current, low junction capacitance, and low substrate-bias coefficient comparable to those of thin-film SOI MOSFET has been developed. The P-SOI MOSFET features a P-N-P channel profile, in which the sandwiched N-type layer is fully depleted by the internal built-in potential. Fabricated 0.25-/spl mu/m P-S...Show More

Pseudo-SOI: P-N-P-channel-doped bulk MOSFET for low-voltage high-performance applications

M. Miyamoto;R. Nagai;T. Nagano

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)

Year: 1998 | Conference Paper |

Hole trapping as the rate-limiting factor in LDD nMOSFET degradation

A. Gupta;D.S. Sugiharto;C.Y. Yang;N. Matsuzaki;M. Minami;T. Yamanaka;T. Nagano

1996 International Integrated Reliability Workshop Final Report

Year: 1996 | Conference Paper |

Cited by: Papers (1)

We have observed a unique phenomenon during low-gate voltage (V/sub G/) static stressing of a CMOS circuit, that was designed for dynamic stressing. Static stressing was performed by probing 0.44 /spl mu/m lightly-doped-drain (LDD) nMOSFET devices that were discrete (isolated), as well as devices that were part of a circuit which consisted of a 301-stage BiCMOS ring-oscillator, followed by a chain...Show More

Hole trapping as the rate-limiting factor in LDD nMOSFET degradation

A. Gupta;D.S. Sugiharto;C.Y. Yang;N. Matsuzaki;M. Minami;T. Yamanaka;T. Nagano

1996 International Integrated Reliability Workshop Final Report

Year: 1996 | Conference Paper |

Asymmetrically-dope buried layer (ADB) structure CMOS for low-voltage mixed analog-digital applications

M. Miyamoto;K. Toyota;K. Sekic;T. Nagano

1996 Symposium on VLSI Technology. Digest of Technical Papers

Year: 1996 | Conference Paper |

Cited by: Papers (2) | Patents (3)

A new CMOS structure is developed distinguished by an asymmetrically-doped buried layer (ADB), which achieves a high transconductance and a high drain output resistance down to 0.3-/spl mu/m technology necessary for high performance analog circuits at low-voltage power supply. The drain output resistance is increased by 50 times at 0.8-/spl mu/m technology and 5.5 times at 0.3-/spl mu/m technology...Show More

Asymmetrically-dope buried layer (ADB) structure CMOS for low-voltage mixed analog-digital applications

M. Miyamoto;K. Toyota;K. Sekic;T. Nagano

1996 Symposium on VLSI Technology. Digest of Technical Papers

Year: 1996 | Conference Paper |

Driving source-line cell architecture for sub-1-V high-speed low-power applications

H. Mizuno;T. Nagano

IEEE Journal of Solid-State Circuits

Year: 1996 | Volume: 31, Issue: 4 | Journal Article |

Cited by: Papers (44) | Patents (4)

A novel SRAM cell architecture for sub-1-V high-speed operation is proposed that uses neither low-V/sub th/ MOSFETs nor modified cell layout patterns. A source-line, connected to the source terminals of the driver MOSFETs is controlled so that it is negative and floating in the read and write cycles, respectively. This improved the bit-line access time by 1/4-1/2 at supply voltages of 0.5-1.0 V. L...Show More

Driving source-line cell architecture for sub-1-V high-speed low-power applications

H. Mizuno;T. Nagano

IEEE Journal of Solid-State Circuits

Year: 1996 | Volume: 31, Issue: 4 | Journal Article |

A 6.93-/spl mu/m/sup 2/ n-gate full CMOS SRAM cell technology with high-performance 1.8-V dual-gate CMOS for peripheral circuits

M. Minami;N. Ohki;H. Ishida;T. Yamanaka;K. Ishibashi;A. Shimizu;T. Kure;T. Nishida;T. Nagano

1995 Symposium on VLSI Technology. Digest of Technical Papers

Year: 1995 | Conference Paper |

Cited by: Papers (2) | Patents (1)

A high-performance microprocessor-compatible small size full CMOS SRAM cell technology has been developed. A 0.3-/spl mu/m gate length load pMOSFET, formed utilizing amorphous-Si-film through-channel implantation, is merged with a 0.25-/spl mu/m gate length pMOSFET for the peripheral circuits. Mask-free contact for TiN local interconnect is developed with wet etching. A 6.93-/spl mu/m/sup 2/ cell ...Show More

A 6.93-/spl mu/m/sup 2/ n-gate full CMOS SRAM cell technology with high-performance 1.8-V dual-gate CMOS for peripheral circuits

M. Minami;N. Ohki;H. Ishida;T. Yamanaka;K. Ishibashi;A. Shimizu;T. Kure;T. Nishida;T. Nagano

1995 Symposium on VLSI Technology. Digest of Technical Papers

Year: 1995 | Conference Paper |

Driving source-line (DSL) cell architecture for sub-1-V high-speed low-power applications

H. Mizuno;T. Nagano

Digest of Technical Papers., Symposium on VLSI Circuits.

Year: 1995 | Conference Paper |

Cited by: Papers (16) | Patents (2)

A novel SRAM cell architecture for sub-1-V high-speed operation is proposed without using either low-V/sub th/ MOSFETs or modifying the cell layout pattern. A source-line connected to the source terminals of driver MOSFETs is controlled to be negative and floating in the read- and write-cycles, respectively. The cell-access time is reduced to 1/4-1/2 at a supply voltage of 0.5-1.0 V. Limiting the ...Show More

Driving source-line (DSL) cell architecture for sub-1-V high-speed low-power applications

H. Mizuno;T. Nagano

Digest of Technical Papers., Symposium on VLSI Circuits.

Year: 1995 | Conference Paper |

A 2-ns, 5-mW, synchronous-powered static-circuit fully associative TLB

H. Higuchi;S. Tachibana;M. Minami;T. Nagano

Digest of Technical Papers., Symposium on VLSI Circuits.

Year: 1995 | Conference Paper |

Cited by: Papers (6)

Virtual memory is used in most high-performance computer systems to extend the address space. Virtual addresses are translated by the system into physical addresses at run-time. The translation is usually accelerated by special hardware called a translation look-aside buffer (TLB). Thus, TLBs are required for high-speed operation. In conventional high-speed TLBs, set-associative memories are utili...Show More

A 2-ns, 5-mW, synchronous-powered static-circuit fully associative TLB

H. Higuchi;S. Tachibana;M. Minami;T. Nagano

Digest of Technical Papers., Symposium on VLSI Circuits.

Year: 1995 | Conference Paper |

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers

K. Ishibashi;K. Takasugi;K. Komiyaji;H. Toyoshima;T. Yamanaka;A. Fukami;N. Hashimoto;N. Ohki;A. Shimizu;T. Hashimoto;T. Nagano;T. Nishida

IEEE Journal of Solid-State Circuits

Year: 1995 | Volume: 30, Issue: 4 | Journal Article |

Cited by: Papers (30) | Patents (16)

A 4-Mb CMOS SRAM with 3.84 /spl mu/m/sup 2/ TFT load cells is fabricated using 0.25-/spl mu/m CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells.<>Show More

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers

K. Ishibashi;K. Takasugi;K. Komiyaji;H. Toyoshima;T. Yamanaka;A. Fukami;N. Hashimoto;N. Ohki;A. Shimizu;T. Hashimoto;T. Nagano;T. Nishida

IEEE Journal of Solid-State Circuits

Year: 1995 | Volume: 30, Issue: 4 | Journal Article |

Trade-offs between CMOS and BiCMOS

Proceedings of 4th International Conference on Solid-State and IC Technology

Year: 1995 | Conference Paper |

This paper describes CMOS/BiCMOS trade-offs for deep sub-micron regime operating at less than 3 V. Advantages of CMOS compatible BiCMOS for high-frequency microprocessors and static random access memories are demonstrated.Show More

Trade-offs between CMOS and BiCMOS

Proceedings of 4th International Conference on Solid-State and IC Technology

Year: 1995 | Conference Paper |

A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL

K. Ishibashi;K. Komiyaji;H. Toyoshima;R. Minami;N. Ohki;H. Ishida;T. Yamanaka;T. Nagano;T. Nishida

IEEE Journal of Solid-State Circuits

Year: 1995 | Volume: 30, Issue: 11 | Journal Article |

Cited by: Papers (5) | Patents (2)

A 4-Mb (64 k/spl times/64) synchronous wave-pipeline CMOS SRAM is fabricated by 0.25-/spl mu/m CMOS technology. Multiphase active pulse control (MPAC) enables fully random 300 MHz operation at 2.5 V, resulting in a bandwidth of 2.4 GB/s. The pulse is generated by multiphase PLL (MPPLL) using an array oscillator with current consumption of 7.5 mA.Show More

A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL

K. Ishibashi;K. Komiyaji;H. Toyoshima;R. Minami;N. Ohki;H. Ishida;T. Yamanaka;T. Nagano;T. Nishida

IEEE Journal of Solid-State Circuits

Year: 1995 | Volume: 30, Issue: 11 | Journal Article |

Advanced TFT SRAM cell technology using a phase-shift lithography

T. Yamanaka;T. Hashimoto;N. Hasegawa;T. Tanaka;N. Hashimoto;A. Shimizu;N. Ohki;K. Ishibashi;K. Sasaki;T. Nishida;T. Mine;E. Takeda;T. Nagano

IEEE Transactions on Electron Devices

Year: 1995 | Volume: 42, Issue: 7 | Journal Article |

Cited by: Papers (27) | Patents (144)

An advanced TFT memory cell technology has been developed for making high-density and high-speed SRAM cells. The cell is fabricated using a phase-shift lithography that enables patterns with spaces of less than 0.25 /spl mu/m to be made using the conventional stepper. Cell area is also reduced by using a small cell-ratio and a parallel layout for the transistor. Despite the small cell-ratio, stabl...Show More

Advanced TFT SRAM cell technology using a phase-shift lithography

T. Yamanaka;T. Hashimoto;N. Hasegawa;T. Tanaka;N. Hashimoto;A. Shimizu;N. Ohki;K. Ishibashi;K. Sasaki;T. Nishida;T. Mine;E. Takeda;T. Nagano

IEEE Transactions on Electron Devices

Year: 1995 | Volume: 42, Issue: 7 | Journal Article |

A 6-ns 4-mb Cmos Sram With Offset-voltage-insensitive Current Sense Amplifiers

K. Ishibashi;K. Ueda;K. Takasugi;K. Komiyaji;H. Toyoshima;T. Yamanaka;A. Fukami;N. Hashimoto;N. Ooki;A. Shimizu;T. Hashimoto;T. Nagano;T. Nishida

Proceedings of 1994 IEEE Symposium on VLSI Circuits

Year: 1994 | Conference Paper |

Cited by: Papers (12)

First Page of the Article

A 6-ns 4-mb Cmos Sram With Offset-voltage-insensitive Current Sense Amplifiers

K. Ishibashi;K. Ueda;K. Takasugi;K. Komiyaji;H. Toyoshima;T. Yamanaka;A. Fukami;N. Hashimoto;N. Ooki;A. Shimizu;T. Hashimoto;T. Nagano;T. Nishida

Proceedings of 1994 IEEE Symposium on VLSI Circuits

Year: 1994 | Conference Paper |

A 2.3/spl mu/m/sup 2/, Single-Bit-Line SRAM Cell with High Soft-Error-Immune Structure

T. Yamanaka;K. Ueda;N. Ohki;N. Hashimoto;T. Hashimoto;A. Shimizu;H. Ishida;T. Nishida;T. Kure;K. Takasugi;K. Sasaki;E. Takeda;T. Nagano

Symposium 1993 on VLSI Technology

Year: 1993 | Conference Paper |

Cited by: Papers (3)

An extremely small SRAM cell technology has been demonstrated, A single-bit-line architecture and planarization technique have: resulted in a 2.3-μm2 cell area. The resistive-gate poly-Si TFT cell enables high soft-error immunity without any additional process steps.

First Page of the Article

A 2.3/spl mu/m/sup 2/, Single-Bit-Line SRAM Cell with High Soft-Error-Immune Structure

T. Yamanaka;K. Ueda;N. Ohki;N. Hashimoto;T. Hashimoto;A. Shimizu;H. Ishida;T. Nishida;T. Kure;K. Takasugi;K. Sasaki;E. Takeda;T. Nagano

Symposium 1993 on VLSI Technology

Year: 1993 | Conference Paper |

Graded-bandgap SiGe Bipolar Transistor Fabricated with Germanium Ion Implantation

Akira Fukami;Ken-ichi Shoji;Takahiro Nagano;Takashi Tokuyama;Cary Y. Yang

ESSDERC '91: 21st European Solid State Device Research Conference

Year: 1991 | Conference Paper |

Cited by: Papers (5) | Patents (2)

A graded-bandgap SiGe heterojunction bipolar transistor (HBT) is fabricated using Ge+ implantation. The maximum current gain and the maximum cutoff frequency are 40 and 8 GHz respectively, while those of the Si control device are 100 and 11 GHz. This relatively high cutoff frequency is obtained for the SiGe HBT despite considerable defects in the emitter and base regions, and is attributed to the ...Show More

Graded-bandgap SiGe Bipolar Transistor Fabricated with Germanium Ion Implantation

Akira Fukami;Ken-ichi Shoji;Takahiro Nagano;Takashi Tokuyama;Cary Y. Yang

ESSDERC '91: 21st European Solid State Device Research Conference

Year: 1991 | Conference Paper |

Increased hot-carrier degradation of NMOSFETs under very fast transient stressing

O. Matsuzaki;A. Watanabe;M. Minami;T. Nagano

29th Annual Proceedings Reliability Physics 1991

Year: 1991 | Conference Paper |

Cited by: Papers (4)

The authors investigate hot-carrier induced degradation of sub-micron NMOSFETs under conditions of drain and gate bias with sub-nanosecond switching times. The results are compared with estimates based on the quasi-static sum of static stresses. Hot-carrier degradation in NMOSFETs subject to sub-nanosecond transient stressing is more severe than estimates based on the quasi-static model suggest. T...Show More

Increased hot-carrier degradation of NMOSFETs under very fast transient stressing

O. Matsuzaki;A. Watanabe;M. Minami;T. Nagano

29th Annual Proceedings Reliability Physics 1991

Year: 1991 | Conference Paper |

A current-mode column comparator circuit for high-speed, low-power on-chip cache-TAG memories

M. Suzuki;S. Tachibana;T. Hayashi;A. Watanabe;T. Nishida;S. Shukuri;H. Higuchi;T. Nagano;K. Shimohigashi

Digest of Technical Papers., 1990 Symposium on VLSI Circuits

Year: 1990 | Conference Paper |

Cited by: Papers (3)

The authors describe a low-power comparator circuit which is especially useful for on-chip cache-TAG memories. A novel TAG memory comparator circuit scheme, called a current-mode column comparator (CMCC) scheme, is proposed, and the low-power nature of the CMCC without degraded accessing speed is described. An experimental 128-entry by 32-b TAG-memory test chip was fabricated using 0.5-μm BiCMOS t...Show More

A current-mode column comparator circuit for high-speed, low-power on-chip cache-TAG memories

M. Suzuki;S. Tachibana;T. Hayashi;A. Watanabe;T. Nishida;S. Shukuri;H. Higuchi;T. Nagano;K. Shimohigashi

Digest of Technical Papers., 1990 Symposium on VLSI Circuits

Year: 1990 | Conference Paper |

A high speed and high reliability MOSFET utilizing an auxiliary gate

M. Minami;Y. Sawahata;H. Matsuki;T. Nagano

Digest of Technical Papers.1990 Symposium on VLSI Technology

Year: 1990 | Conference Paper |

Cited by: Papers (2)

For future submicron MOSFETs, the realization of both high speed and high reliability is becoming more and more difficult. A conventional LDD structure is not adequately reliable for future submicron MOSFETs due to the high electric field in the vicinity of the drain junction. To decrease the electric field, gate-overlap LDD (GOLDD) structures have been proposed. However, these structures have lar...Show More

A high speed and high reliability MOSFET utilizing an auxiliary gate

M. Minami;Y. Sawahata;H. Matsuki;T. Nagano

Digest of Technical Papers.1990 Symposium on VLSI Technology

Year: 1990 | Conference Paper |

A 3.5-ns, 500-mW, 16-kbit BiCMOS ECL RAM

M. Suzuki;S. Tachibana;A. Watanabe;S. Shukuri;H. Higuchi;T. Nagano;K. Shimohigashi

IEEE Journal of Solid-State Circuits

Year: 1989 | Volume: 24, Issue: 5 | Journal Article |

Cited by: Papers (17) | Patents (1)

A 16-kbit BiCMOS ECL SRAM with a typical address access time of 3.5 ns and 500-mW power dissipation was developed. The RAM was fabricated using half-micrometer, triple-poly, and triple-metal BiCMOS technology. The fast access time with moderate power dissipation has been achieved using new circuit techniques: a grounded-gate, nonlatching-type level converter with a wired-OR predecoder and a direct...Show More

A 3.5-ns, 500-mW, 16-kbit BiCMOS ECL RAM

M. Suzuki;S. Tachibana;A. Watanabe;S. Shukuri;H. Higuchi;T. Nagano;K. Shimohigashi

IEEE Journal of Solid-State Circuits

Year: 1989 | Volume: 24, Issue: 5 | Journal Article |

Future BiCMOS technology for scaled supply voltage

A. Watanabe;T. Nagano;S. Shukuri;T. Ikeda

International Technical Digest on Electron Devices Meeting

Year: 1989 | Conference Paper |

Cited by: Papers (42) | Patents (3)

A BiCMOS technology for future scaled supply voltage, V/sub x/, is described. Delay time reduction by around 100 ps is achieved by introducing a proposed base electrode surround emitter transistor (BEST). Two types of gates, CBiCMOS and BiNMOS, provide shorter gate delays and higher drivabilities than the CMOS gate even with V/sub s/, of 3.3 V. It is concluded that the innovations in the bipolar t...Show More

Future BiCMOS technology for scaled supply voltage

A. Watanabe;T. Nagano;S. Shukuri;T. Ikeda

International Technical Digest on Electron Devices Meeting

Year: 1989 | Conference Paper |

A 3.5 ns, 500 mW 16 kb BiCMOS ECL RAM

M. Suzuki;S. Tachibana;A. Watanabe;S. Shukuri;H. Higuchi;T. Nagano;K. Shimohigashi

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

Year: 1989 | Conference Paper |

Cited by: Papers (18) | Patents (5)

A 16-Kb RAM was designed and fabricated using a 0.5- mu m BiCMOS technology. It has a typical address access time of 3.5 ns. The RAM operates at a supply voltage of -4.5 V and features 500-mW power dissipation. A description is given of two techniques crucial to high-speed, low-power design: a wired -OR precoder combined with a low-power, high-speed level converter circuit and a direct column-sens...Show More

A 3.5 ns, 500 mW 16 kb BiCMOS ECL RAM

M. Suzuki;S. Tachibana;A. Watanabe;S. Shukuri;H. Higuchi;T. Nagano;K. Shimohigashi

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

Year: 1989 | Conference Paper |

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