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A 6-ns 4-mb Cmos Sram With Offset-voltage-insensitive Current Sense Amplifiers
K. Ishibashi;K. Ueda;K. Takasugi;K. Komiyaji;H. Toyoshima;T. Yamanaka;A. Fukami;N. Hashimoto;N. Ooki;A. Shimizu;T. Hashimoto;T. Nagano;T. Nishida
Proceedings of 1994 IEEE Symposium on VLSI Circuits
Year: 1994 | Conference Paper |
Cited by: Papers (12)
First Page of the Article
Show MoreA 2.3/spl mu/m/sup 2/, Single-Bit-Line SRAM Cell with High Soft-Error-Immune Structure
T. Yamanaka;K. Ueda;N. Ohki;N. Hashimoto;T. Hashimoto;A. Shimizu;H. Ishida;T. Nishida;T. Kure;K. Takasugi;K. Sasaki;E. Takeda;T. Nagano
An extremely small SRAM cell technology has been demonstrated, A single-bit-line architecture and planarization technique have: resulted in a 2.3-μm2 cell area. The resistive-gate poly-Si TFT cell enables high soft-error immunity without any additional process steps.
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First Page of the Article
Show MoreA 16 Mb CMOS SRAM with a 2.3 mu m/sup 2/ single-bit-line memory cell
K. Sasaki;K. Ueda;K. Takasugi;H. Toyoshima;T. Yamanaka;N. Hashimoto;N. Ohki
1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers
Year: 1993 | Conference Paper |
Cited by: Patents (3)
A 16-Mb CMOS SRAM (static random access memory) that uses a 2.3- mu m/sup 2/ single-bit-line poly-pMOS load memory cell is presented. A write/read architecture for a high-density poly-pMOS load (or poly-resistor load) single-bit-line cell is used. The single-bit-line cell reduces the cell area to two thirds that of a two-bit-line cell using the same metal process. The 16-Mb SRAM, a test chip for a...Show More
A 16-Mb CMOS SRAM with a 2.3- mu m/sup 2/ single-bit-line memory cell
K. Sasaki;K. Ueda;K. Takasugi;H. Toyoshima;K. Ishibashi;T. Yamanaka;N. Hashimoto;N. Ohki
A novel architecture that enables fast write/read in poly-PMOS load or high-resistance polyload single-bit-line cells is developed. The architecture for write uses alternate twin word activation (ATWA) with bit-line pulsing. A dummy cell is used to obtain a reference voltage for reading. An excellent balance between a normal cell signal line and a dummy cell signal line is attained using balanced ...Show More
A 7 ns 140 mW 1 Mb CMOS SRAM with current sense amplifier
K. Sasaki;K. Ishibashi;K. Ueda;K. Komiyaji;T. Yamanaka;N. Hashimoto;H. Toyoshima;F. Kojima;A. Shimizu
1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers
Year: 1992 | Conference Paper |
A 1-Mb CMOS SRAM uses a high-speed current-sense amplifier and a pre-output buffer designed for 3-V power supply to achieve 7-ns access and 140-mW power dissipation. A 6.6- mu m/sup 2/ cell is achieved using 0.3- mu m CMOS technology with phase-shifting photolithography. Soft-error immunity can be drastically improved by the cross-coupled resistances built into the polysilicon pMOS transistors wit...Show More
A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier
K. Sasaki;K. Ishibashi;K. Ueda;K. Komiyaji;T. Yamanaka;N. Hashimoto;H. Toyoshima;F. Kojima;A. Shimizu
A 7-ns 140-mW 1-Mb CMOS SRAM was developed to provide fast access and low power dissipation by using high-speed circuits for a 3-V power supply: a current-sense amplifier and pre-output buffer. The current-sense amplifier shows three times the gain of a conventional voltage-sense amplifier and saves 60% of power dissipation while maintaining a very short sensing delay. The pre-output buffer reduce...Show More
A 15-ns 1-Mbit CMOS SRAM
K. Sasaki;S. Hanamura;K. Ueda;T. Oono;O. Minato;Y. Sakai;S. Meguro;M. Tsunematsu;T. Masuhara;M. Kubotera;H. Toyoshima
A 1-Mb CMOS static RAM with a 256 K word*4-bit configuration has been developed. The RAM was fabricated using 0.8- mu m double-poly and double-aluminum twin-well CMOS technology. A small cell size of 5.2 mu m*8.5 mu m and a chip size of 6.15 mm*15.21 mm have been achieved. A fast address access time of 15 ns was achieved using novel circuit techniques: a PMOS-load decoder and a three-stage dynamic...Show More
Performance Study of the Whole-Body, Multilayer Positron Computed Tomograph. - PCTW-II -
K. Okajima;K. Ueda;K. Takami;K. Ishimatsu;T. Hayashi;K. Torizuka
A whole body Positron CT has been developed. The system has a gantry consisting of 4 detector-rings and provides 7 slice-images simultaneously. The continuously rotating scan method is employed in this system. Each detector-ring consists of 192 gamma-ray detectors using BGO scintillation crystals (12×24×24 mm). A dual rectangular photomultiplier tube has been developed to increase the detector pac...Show More
Performance Study of Whole-Body, Multislice Positron Computed Tomograph POSITOLOGICA-II
K. Takami;K. Ueda;K. Okajima;E. Tanaka;N. Nohara;T. Tomitani;M. Yamamoto;H. Murayama;F. Shishido;K. Ishimatsu;A. Ohgushi;S. Inoue;Y. Takakusa;T. Hayashi;S. Nakase
A 3-detector ring, 5-slice whole-body positron CT has been developed and is being tested. The PCT, POSITOLOGICA-II, has a total of 480 BGO's (160/ring), and employs continuous rotation scan (0.5rps). By using a 15mm wide BGO, a 9.2mm FWHM spatial resolution for reconstructed image is obtained at the center of FOV. Measured phantom diameter dependence of the true count rate shows good agreement wit...Show More
Evaluation of Slice Shield Collimators for Multi-Layer Positron Emission Computed Tomographs
Ken Ueda;Eiichi Tanaka;Katsumi Takami;Fumio Kawaguchi;Kenichi Okajima;Kenji Ishimatsu
Evaluation of slice shield collimators is carried out using theoretical event rate formulas. This approach permits calculation of system performance in terms of sensitivity, scatter fraction, and high-counting rate characteristics. Electronics counting efficiency is also taken into account. A rational approach to optimal design is presented along with design examples. Effectiveness of collimator r...Show More
Design Consideration for a Continuously Rotating Positron Computed Tomograph
K. Takami;K. Ishimatsu;T. Hayashi;K. Ueda;F. Kawaguchi;K. Okajima;A. Ohgushi;S. Inoue;Y. Takakusa;S. Nakase;E. Tanaka
Design consideration for a whole-body, multislice Positron CT having 3 detector rings, 160 BGO crystal/ring, and a continuously rotating scan is described. The one detector ring has 40 "BGO Quad-detectors", each of which consists of 4 BGO crystals and two photomultipliers. Improvements in the BGO crystal and the photomultiplier have been accomplished. Geometrical configuration of the collimator wa...Show More
Positologica: A Positron ECT Device with a Continuously Rotating Detector Ring
Norimasa Nohara;Eiichi Tanaka;Takehiro Tomitani;Mikio Yamamoto;Hideo Murayama;Yoshio Suda;Masahiro Endo;Takeshi Iinuma;Yukio Tateno;Fumio Shishido;Kenji Ishimatsul;Ken Ueda;Katsumi Takami
A rotary positron emission computed tomography device is developed for human brain and animal studies. The device utilizes 64 rectangular BGO detectors arranged at unequal spacing on a circular ring. The detector ring is continuously rotated at a constant speed of 60 rpm or less. This single continuous motion of the ring with the detector array provides excellent sampling characteristics and high ...Show More
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