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Showing 1-25 of 67,011 resultsfor "Index Terms":digital-to-analog converter
"Index Terms":digital-to-analog converter
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Design of power efficient hybrid flash-successive approximation register analog to digital converter
2017 International Conference on Communication and Signal Processing (ICCSP)
Year: 2017 | Conference Paper |
Cited by: Papers (2)
The need for a high speed and low power ADC is very essential for various applications. This paper presents a new hybrid analog-to-digital convertor (ADC) combining a capacitive digital-to-analog (CDAC) based multi-bit/cycle successive approximation (SAR) ADC with a flash ADC. As portable terminals demand long battery and high sampling rate. Handheld equipment's for wireless like WI-FI and WI-MAX ...Show More
A 28GS/s 6b pseudo segmented current steering DAC in 90nm CMOS
Thomas Alpert;Felix Lang;Damir Ferenci;Markus Grözing;Manfred Berroth
2011 IEEE MTT-S International Microwave Symposium
Year: 2011 | Conference Paper |
Cited by: Papers (9)
A pseudo segmented twofold time-interleaved 6-bit digital-to-analog converter (DAC) occupies 0.28 mm2 chip area in a standard 90 nm CMOS technology. The DAC enables sampling rates up to 28 GS/s with a power consumption of 2.25 W at a −2.5 V power supply. The output bandwidth is at least 14 GHz. The integral non-linearity (INL) and the differential non-linearity (DNL) are 0.8 LSB and 1 LSB respecti...Show More
A 0.35μm CMOS 6-bit current steering DAC
Anand Narayanan;Mikael Bengtsson;Rengarajan Ragavan;Quoc-Tai Duong
2013 European Conference on Circuit Theory and Design (ECCTD)
Year: 2013 | Conference Paper |
Cited by: Papers (2)
This paper presents the design and experimental results of a high speed, low-power, thermometer coded and current steered 6-bit digital-to-analog converter (DAC). It is based on a hybrid architecture with a switched current matrix controlled by the four most significant digital bits, and a conventional 2-bit current source controlled by the two least significant bits. The DAC occupies 0.15 mm2 chi...Show More
A 10bit 1.6GS/s Current-steering DAC in 40nm CMOS
2021 IEEE 14th International Conference on ASIC (ASICON)
Year: 2021 | Conference Paper |
In this paper, systematic design of a 10bit 1.6GS/s current-steering (CS) digital-to-analog converter (DAC) is presented. Both two-stage decoder and three latch stages are applied to synchronize input data. To guarantee matching, all bits are implemented by parallel or series of unit current cells; double centroid floorplan and balanced-ring switching are adopted in the layout design. Post-simulat...Show More
A to-bit 100-MHz Current-Steering DAC with Randomized Thermometer Code Calibration Scheme
2019 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)
Year: 2019 | Conference Paper |
This paper presents a 10-bit 100 MHz digital-to-analog converter (DAC) by using a current-steering architecture. The proposed DAC suits for high speed and high resolution applications. Since the current-steering DAC suffers from the process mismatch which limits both the static and dynamic performances, this work employs a pseudo-random controller to improve the linearity. The random generator con...Show More
A 1.2V 10-bit 500-MS/s current steering DAC in 90nm technology
2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)
Year: 2016 | Conference Paper |
Digital-to-Analog converter (DAC) is a fundamental device in data processing systems. It serves as a conversion interface to reconstruct the analog signal from the digital output of the signal processors. In this work, the design and implementation of a 10-bit Segmented Current Steering DAC is carried out at 500 MHz clock frequency and 1.2 V supply voltage. The Segmented architecture provides the ...Show More
A novel current estimation technique for digital controlled switching converters operating in CCM and DCM
2017 IEEE Energy Conversion Congress and Exposition (ECCE)
Year: 2017 | Conference Paper |
Cited by: Papers (10)
Inductor current in the high speed switching converters is used as a feedback signal for current mode control and over current fault protection. Sensing inductor current for the use of digital controllers require high bandwidth current sensors and also need high speed Analog to Digital Converter (ADC) to convert the sensed current into digital domain. Use of high bandwidth current sensors and high...Show More
A Low-Power and Area-Efficient 14-bit SAR ADC with Hybrid CDAC for Array Sensors
2019 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2019 | Conference Paper |
Cited by: Papers (4)
This paper proposes a low-power and area efficient 14-bit Successive Approximation Register (SAR) analog-to-digital converter (ADC) for array sensors. A hybrid capacitor digital-to-analog converter (CDAC), which consist of a 10-bit split CDAC and a 5-bit serial CDAC, is utilized to increase the area efficiency. The total required number of unit capacitors are only 52. A foreground digital calibrat...Show More
Glitch Energy Reduction and SFDR Enhancement Techniques for Low-Power Binary-Weighted Current-Steering DAC
This brief proposes a glitch reduction approach by dynamic capacitance compensation of binary-weighted current switches in a current-steering digital-to-analog converter (DAC). The method was proved successfully by a 10-bit 400-MHz pure binary-weighted current-steering DAC with a minimum number of retiming latches. The experiment results yield very low-glitch energy during major carry transitions ...Show More
A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm $^{2}$
Si-Nai Kim;Mee-Ran Kim;Ba-Ro-Saim Sung;Hyun-Wook Kang;Min-Hyung Cho;Seung-Tak Ryu
A 6-bit full-binary compact and low-power current-steering digital-to-analog converter (DAC) designed for 60-GHz Wireless Personal Area Network applications is presented. The closely located circuit components based on the stacked unit cell minimize the parasitic capacitance and enhance the high-frequency dynamic linearity. The proposed binary structure realizes a compact DAC by eliminating the ne...Show More
An Area-Efficient High-Resolution Resistor-String DAC with Reverse Ordering Scheme for Active Matrix Flat-Panel Display Data Driver ICs
Journal of Display Technology
Cited by: Papers (19)
In this paper, we propose an area-efficient high-resolution resistor-string digital-to-analog converter (R-DAC) with a reverse ordering scheme for active matrix flat-panel display data driver ICs. The proposed R-DAC is implemented in a two-stage DAC along with a DAC-embedded amplifier. The reverse ordering scheme reduces the area of the proposed R-DAC, which occupies most of the area of the data d...Show More
A Highly Linear 10-Bit DAC of Data Driver IC Using Source Degeneration Load for Active Matrix Flat-Panel Displays
This brief proposes a highly linear digital-to-analog converter (DAC) of the data driver IC for active matrix flat-panel displays (AMFPDs). The proposed 10-bit two-stage DAC is realized with an upper 6-bit decoder and a lower 4-bit DAC-embedded amplifier. The decoder in the first stage selects two adjacent voltages from among the reference voltages of the R-string according to the upper 6-bit. The...Show More
Cryogenic Current Steering DAC With Mitigated Variability
Marcos E. P. V. Zurita;Loïck Le Guevel;Gérard Billiot;Adrien Morel;Xavier Jehl;Aloysius G. M. Jansen;Gaël Pillonnet
This letter presents an 8-b differential current steering digital-to-analog converter (DAC) for the cryogenic front-end of future quantum computers. Recently published characterization of CMOS technology reveals the deterioration of transistor matching properties at cryogenic temperatures. The preliminary study of the current mismatch in the FDSOI technology at 4.2 K allows proper sizing of the 25...Show More
High SFDR Current-Steering DAC With Splitting-and-Binary Segmented Architecture and Dynamic-Element-Matching Technique
This brief presents a current-steering digital-to-analog converter (DAC) with “4-bit splitting +8-bit binary” segmented topology. The proposed splitting decoding method can optimize the differential nonlinearity and output glitches of the DAC with a more simplified circuit scale than unary decoding. With a data-transmission topology, the splitting decoder has a low latency and accommodates fast sy...Show More
Secure Rate Maximization for Reconfigurable Intelligent Surface Assisted Transmission with Low-resolution DACs
2021 7th International Conference on Computer and Communications (ICCC)
Year: 2021 | Conference Paper |
Cited by: Papers (1)
This paper investigates the secrecy rate of multiple reconfigurable intelligent surfaces (RISs)-assisted millimeter wave system with low-resolution digital-to-analog converters, where a base station (BS) serves a single-antenna user while a single-antenna eavesdropper wiretapping the information sent to the user. To reduce energy consumption, the RIS that can provide maximal secrecy rate is select...Show More
A 133.3 dB Dynamic Range Pulse Oximeter Front-End with Low-Noise Area-Efficient Offset Cancellation Current DAC
2023 International Conference on Electronics, Information, and Communication (ICEIC)
Year: 2023 | Conference Paper |
This paper introduces a pulse oximeter front-end with low-noise area-efficient offset cancellation current digital-to-analog converter (DAC). The proposed offset cancellation current DAC is implemented to cancel the input DC current to improve the effective dynamic range (DR). The current DAC is designed to have low-noise and area-efficient characteristics by applying the dynamic element matching ...Show More
According to the segmented current steering Digital-to-analog converter (DAC), the influence of current mismatch and output impedance of the current array on the linearity of DAC is discussed by theoretical analysis and derivation. An optimized layout plan for the current source array randomizes all these unit current sources corresponding to each thermometer code, which can significantly reduce t...Show More
High-Speed A/D & D/A conversion: A survey
2008 IEEE Bipolar/BiCMOS Circuits and Technology Meeting
Year: 2008 | Conference Paper |
Cited by: Papers (5)
This paper deals with general discussion over high-speed data converter architectures. Nowadays, more and more researches are focused on the ability to design transceivers able to manage digital data as soon as possible right behind the antenna. These so-called Software Defined Radio architectures are one of the easiest ways to design a receiver with low time-to-market impact. Furthermore, most of...Show More
An Energy-Efficient Low Frequency-Dependence Switching Technique for SAR ADCs
This brief presents a highly energy-efficient switching scheme for successive approximation register (SAR) analog-to-digital converters that achieves a 95% reduction in switching energy over the conventional SAR. The switching energy has been calculated by taking into account both the power drawn from reference and the power consumed by the switches themselves. The frequency dependence of the swit...Show More
Dithering Loopback-Based Prediction Technique for Mixed-Signal Embedded System Specifications
Lower cost test solutions are required to overcome high test cost issue of conventional characterization for the mixed-signal circuits, which is primarily caused by test equipment cost. This brief proposes a cost-effective self-characterization technique that accurately predicts the harmonics of individual mixed-signal circuits by dithering a loopback path with Gaussian-distributed noise. A set of...Show More
Toward Accurate Analysis of Channel Charge Injection in SAR ADCs' Capacitive DACs
Alireza Ahrar;Jianxiong Xu;Mohammad Reza Pazhouhandeh;Antoine Frappe;Mostafa Rahimi Azghadi;Amirali Amirsoleimani
2024 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2024 | Conference Paper |
This paper conducts a detailed analysis of the impact of channel charge injection on the capacitive digital-to-analog (DAC) block in successive-approximation register (SAR) analog-to-digital converters (ADCs). It introduces a CAD tool for distinguishing various non-idealities, quantifying channel charge injection across all possible binary output codes. It enables the implementation of more effect...Show More
A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees
Shahriar Shahramian;Sorin P. Voinigescu;Anthony Chan Carusone
This paper presents a 35-GS/s, 4-bit flash ADC-DAC with active data and clock distribution trees. At mm-wave clock frequencies, skew due to mismatch in the clock and data distribution paths is a significant challenge for both flash and time-interleaved converter architectures. A full-rate front-end track and hold amplifier (THA) may be used to reduce the effect of skew. However, it is found that t...Show More
Research on UWB OFDM signal conversion
Yingxin Zhao;Lijun Ge;Shuang Wang;Yuang Jin;Minhao Fu;Hong Wu
2010 IEEE International Conference on Intelligent Computing and Intelligent Systems
Year: 2010 | Conference Paper |
This paper presents a multi-bit discrete time sigma-delta converter for orthogonal frequency division multiplexing ultra wide band systems adopted by IEEE 802.15.3a and ECMA368 standard. An intact scheme of timing synchronization algorithm is also proposed for the receiver. The overall sigma-delta converter consists of two modulators. The low and high subbands of signal are operated by using third...Show More
A 6-bit segmented RZ DAC architecture with up to 50-GHz sampling clock and 4 Vpp differential swing
2012 IEEE/MTT-S International Microwave Symposium Digest
Year: 2012 | Conference Paper |
A novel, distributed, return-to-zero (RZ) power digital-to-analog converter (DAC) architecture is presented. The circuit features 14 independent data bits - 7 for the 3 most significant bits (MSB) and 7 for the 3 least significant bits (LSB) - each running at up to 50 Gb/s. It is fabricated in a production 130-nm SiGe BiCMOS technology and operates as a large swing arbitrary waveform generator sui...Show More
A 2GSps 12bit DAC with SFDR >57.5dBc up to Nyquist bandwidth
2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)
Year: 2013 | Conference Paper |
Cited by: Papers (5)
In this paper we present a 2GSps 12bit current steering digital-to-analog converter (DAC), in 100G Ft 0.18µm SiGe HBT technology. An improved switching sequence is proposed to compensate the gradient error and reduce the impact of cell-dependent-delay-variation. According to measured results, the test chip achieved a DNL/INL of 0.6/0.95 LSB respectively. The measured SFDR at low frequency is above...Show More
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