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Hyun-Wook Kang - IEEE Xplore Author Profile
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Hyun-Wook Kang

Also published under: Hyunwook Kang, Hyun Wook Kang

Publications
13
Citations
307
Publications by Year
20082020
Co-Authors:
Show All Co-Authors (38)
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Hyun-Wook Kang

Also published under: Hyunwook Kang, Hyun Wook Kang

Affiliation

Samsung Advanced Institute of Technology, Suwon, South Korea

Publication Topics

Biography

Hyun-Wook Kang received the B.S. degree (with high Hons.) in electrical engineering and computer sciences from the University of California, Berkeley, CA, USA, in 2011, and the M.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology, Daejeon, South Korea, in 2013, where he is currently pursuing the Ph.D. degree.,His current research interests include power-efficient data converter and mixed-signal circuit designs.(Based on document published on 21 June 2018).
Publications
13
Citations
307
Publications by Year
20082020
Co-Authors:
Show All Co-Authors (38)
Author's Published Works

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A 62dB-SNDR 40.2μW 10MS/s ADC for Power Efficient IoT and Biomedical Read-Out Systems

Hyeok-Ki Hong;Hyun-Wook Kang;Che-Heung Kim

2020 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2020 | Conference Paper |
Cited by: Papers (1)
This paper presents a power and area efficient architecture for the Internet of Things (IoT) and biomedical sensor read-out applications. The architecture adopts step-wise charging to support voltage stacking power delivery solution for digital processors. MSB floating decision scheme with bottom-plate sampling is adopted for low power and reduced decision error. The errors from floating decision ...Show More

A 62dB-SNDR 40.2μW 10MS/s ADC for Power Efficient IoT and Biomedical Read-Out Systems

Hyeok-Ki Hong;Hyun-Wook Kang;Che-Heung Kim

Year: 2020 | Conference Paper |

A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme

Hyun-Wook Kang;Hyeok-Ki Hong;Wan Kim;Seung-Tak Ryu

IEEE Journal of Solid-State Circuits
Year: 2018 | Volume: 53, Issue: 9 | Journal Article |
Cited by: Papers (33)
This paper presents a two-way time-interleaved (TI) 12-b 270-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a virtual-timing-reference timing-skew calibration scheme, in which the timing-skew calibration spurs present in conventional calibration schemes are effectively suppressed with the deferred reference sampling edge. The proposed design runs in a true back...Show More

A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme

Hyun-Wook Kang;Hyeok-Ki Hong;Wan Kim;Seung-Tak Ryu

Year: 2018 | Volume: 53, Issue: 9 | Journal Article |

A 9.1 ENOB 21.7fJ/conversion-step 10b 500MS/s single-channel pipelined SAR ADC with a current-mode fine ADC in 28nm CMOS

Kyoung-Jun Moon;Hyun-Wook Kang;Dong-Shin Jo;Mi-Young Kim;Seung-Yeob Baek;Michael Choi;Hyung-Jong Ko;Seung-Tak Ryu

2017 Symposium on VLSI Circuits
Year: 2017 | Conference Paper |
A single-channel 10b pipelined SAR ADC with a gm-cell residue amplifier and a current-mode fine SAR ADC achieves a 500MS/s conversion rate in a 28nm CMOS process under a 1.0 V supply. With background offset and gain calibration, the prototype ADC achieves an SNDR of 56.6dB at Nyquist. With power consumption of 6mW, it obtains a FoM of 21.7fJ/conversion-step.Show More

A 9.1 ENOB 21.7fJ/conversion-step 10b 500MS/s single-channel pipelined SAR ADC with a current-mode fine ADC in 28nm CMOS

Kyoung-Jun Moon;Hyun-Wook Kang;Dong-Shin Jo;Mi-Young Kim;Seung-Yeob Baek;Michael Choi;Hyung-Jong Ko;Seung-Tak Ryu

Year: 2017 | Conference Paper |

A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC

Wan Kim;Hyeok-Ki Hong;Yi-Ju Roh;Hyun-Wook Kang;Sun-Il Hwang;Dong-Shin Jo;Dong-Jin Chang;Min-Jae Seo;Seung-Tak Ryu

IEEE Journal of Solid-State Circuits
Year: 2016 | Volume: 51, Issue: 8 | Journal Article |
This paper presents an asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC as a suitable architecture in a low-supply-voltage condition. Settling-While-Conversion enabled by the Assist-ADC relaxes the DAC settling time requirement and makes it possible to insert a minimized capacitor shuffling logic with no speed penalty. A proposed gain-boosting dynamic pre-amplifier enhances the noise ...Show More

A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC

Wan Kim;Hyeok-Ki Hong;Yi-Ju Roh;Hyun-Wook Kang;Sun-Il Hwang;Dong-Shin Jo;Dong-Jin Chang;Min-Jae Seo;Seung-Tak Ryu

Year: 2016 | Volume: 51, Issue: 8 | Journal Article |

A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs

Hyun-Wook Kang;Hyeok-Ki Hong;Sanghoon Park;Ki-Jin Kim;Kwang-Ho Ahn;Seung-Tak Ryu

IEEE Transactions on Circuits and Systems II: Express Briefs
Year: 2016 | Volume: 63, Issue: 6 | Journal Article |
A background timing-mismatch calibration algorithm is proposed, which detects and corrects the sampling time mismatches in time-interleaved analog-to-digital converter (ADC) channels by analyzing the sign-equality of a reference slope and a timing-mismatch-induced error value. The sign of the ideal derivative along the input is estimated through the adjacent channel outputs, thus not requiring an ...Show More

A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs

Hyun-Wook Kang;Hyeok-Ki Hong;Sanghoon Park;Ki-Jin Kim;Kwang-Ho Ahn;Seung-Tak Ryu

Year: 2016 | Volume: 63, Issue: 6 | Journal Article |

A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm $^{2}$

Si-Nai Kim;Mee-Ran Kim;Ba-Ro-Saim Sung;Hyun-Wook Kang;Min-Hyung Cho;Seung-Tak Ryu

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year: 2016 | Volume: 24, Issue: 2 | Journal Article |
Cited by: Papers (16)
A 6-bit full-binary compact and low-power current-steering digital-to-analog converter (DAC) designed for 60-GHz Wireless Personal Area Network applications is presented. The closely located circuit components based on the stacked unit cell minimize the parasitic capacitance and enhance the high-frequency dynamic linearity. The proposed binary structure realizes a compact DAC by eliminating the ne...Show More

A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm $^{2}$

Si-Nai Kim;Mee-Ran Kim;Ba-Ro-Saim Sung;Hyun-Wook Kang;Min-Hyung Cho;Seung-Tak Ryu

Year: 2016 | Volume: 24, Issue: 2 | Journal Article |

A 2.6b/cycle-Architecture-Based 10b 1.7GS/s 15.4mW 4x-Time-Interleaved SAR ADC with a Multistep Hardware-Retirement Technique

Hyeok-Ki Hong;Hyun-Wook Kang;Dong-Shin Jo;Dong-Suk Lee;Yong-Sang You;Yong-Hee Lee;Ho-Jin Park;Seung-Tak Ryu

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers
Year: 2015 | Conference Paper |
With the growing interest in time-interleaved (TI) structures, the conversion rates of ADCs have greatly improved, which has inevitably increased power consumption. Despite the advantages of TI structures, power consumption is increased due to the stricter matching requirements between channels; in some cases, >50% of total power is for calibration purposes. Thus, to realize high-speed and high-re...Show More

A 2.6b/cycle-Architecture-Based 10b 1.7GS/s 15.4mW 4x-Time-Interleaved SAR ADC with a Multistep Hardware-Retirement Technique

Hyeok-Ki Hong;Hyun-Wook Kang;Dong-Shin Jo;Dong-Suk Lee;Yong-Sang You;Yong-Hee Lee;Ho-Jin Park;Seung-Tak Ryu

Year: 2015 | Conference Paper |

A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC

Hyeok-Ki Hong;Wan Kim;Hyun-Wook Kang;Sun-Jae Park;Michael Choi;Ho-Jin Park;Seung-Tak Ryu

IEEE Journal of Solid-State Circuits
Year: 2015 | Volume: 50, Issue: 2 | Journal Article |
Cited by: Papers (79)
A compact decision-error-tolerant 2b/cycle SAR ADC architecture is presented. Two DACs with different designated functions, SIG-DAC and REF-DAC, are implemented to make the structure compact and to eliminate the sampling skew issue. Use of a nonbinary decision scheme with decision redundancies not only increases the ADC speed with a relaxed DAC settling requirement but also makes the performance r...Show More

A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC

Hyeok-Ki Hong;Wan Kim;Hyun-Wook Kang;Sun-Jae Park;Michael Choi;Ho-Jin Park;Seung-Tak Ryu

Year: 2015 | Volume: 50, Issue: 2 | Journal Article |

A Replica-Driving Technique for High Performance SC Circuits and Pipelined ADC Design

Chang-kyo Lee;Wan Kim;Hyunwook Kang;Seung-Tak Ryu

IEEE Transactions on Circuits and Systems II: Express Briefs
Year: 2013 | Volume: 60, Issue: 9 | Journal Article |
Cited by: Papers (15)
This paper proposes a replica-driving technique that can be applied to implement low-power high-performance switched-capacitor (SC) amplifiers. The reduced swing range problem arising from the output-stage source-follower is resolved by a simple SC level shifter, without additional supply or static buffer. The output driving capability is enhanced by using a capacitively-controlled class-AB output...Show More

A Replica-Driving Technique for High Performance SC Circuits and Pipelined ADC Design

Chang-kyo Lee;Wan Kim;Hyunwook Kang;Seung-Tak Ryu

Year: 2013 | Volume: 60, Issue: 9 | Journal Article |

An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement

Hyeok-Ki Hong;Hyun-Wook Kang;Barosaim Sung;Choong-Hoon Lee;Michael Choi;Ho-Jin Park;Seung-Tak Ryu

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers
Year: 2013 | Conference Paper |
By taking advantage of the merits of the low power consumption and hardware simplicity of SAR ADCs, 2b/cycle conversion structures in SAR ADCs have been actively studied in recent years for enhanced conversion rates and excellent FoM [1-3]. However, many error sources in the 2b/cycle SAR ADCs, such as mismatches between DACs and comparators, and the signal-dependent errors from comparators, namely...Show More

An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement

Hyeok-Ki Hong;Hyun-Wook Kang;Barosaim Sung;Choong-Hoon Lee;Michael Choi;Ho-Jin Park;Seung-Tak Ryu

Year: 2013 | Conference Paper |

High-Performance Pentacene Thin-Film Transistors Fabricated by Organic Vapor-Jet Printing

Changhun Yun;Hanul Moon;Hyun Wook Kang;Mincheol Kim;Hyung Jin Sung;Seunghyup Yoo

IEEE Electron Device Letters
Year: 2010 | Volume: 31, Issue: 11 | Journal Article |
Cited by: Papers (4)
Organic vapor-jet printing, a maskless direct printing method, is used to fabricate high-performance pentacene thin-film transistors. By combining the optimal carrier gas temperature and the surface treatment of gate dielectrics, a mobility of 0.46 (±0.03) cm2 V-1 s-1 and an on-off ratio greater than 107 are achieved. Morphological analyses indicate that the relatively high carrier gas temperature...Show More

High-Performance Pentacene Thin-Film Transistors Fabricated by Organic Vapor-Jet Printing

Changhun Yun;Hanul Moon;Hyun Wook Kang;Mincheol Kim;Hyung Jin Sung;Seunghyup Yoo

Year: 2010 | Volume: 31, Issue: 11 | Journal Article |

Non-Newtonian effect on ink transfer for gravureoffset printing

Dewan Hasan Ahmed;Hyun Wook Kang;Hyung Jin Sung

2009 IEEE International Symposium on Assembly and Manufacturing
Year: 2009 | Conference Paper |
Cited by: Papers (1)
A computational simulation is carried out with the Carreau model to explore the non-Newtonian behavior of ink for gravure-offset printing. The volume of fluid (VOF) model is adopted to demonstrate the stretching and breakup behaviors of ink. The results indicate that the ink transfer ratio is much influenced by contact angle especially by the contact angle of upper plate (¿). The ink transfer of n...Show More

Non-Newtonian effect on ink transfer for gravureoffset printing

Dewan Hasan Ahmed;Hyun Wook Kang;Hyung Jin Sung

Year: 2009 | Conference Paper |

Development of Rapid Mask Fabrication Technology for Micro-Abrasive Machining

In Hwan Lee;Seung Pyo Lee;Tae Jo Ko;Hyun Wook Kang;Dong-Woo Cho

2008 International Conference on Smart Manufacturing Application
Year: 2008 | Conference Paper |
Cited by: Papers (2)
Micro-abrasive jet machining (mu-AJM) has become a useful technique for micro-machining of a brittle material such as glass, silicon, etc. This technology is mainly based on the erosion of a mask which protects substrate against high velocity of micro-particles. Generally, for the fabrication of a mask in the mu-AJM process, a photomask based on the semi-conductor fabrication process was used. In ...Show More

Development of Rapid Mask Fabrication Technology for Micro-Abrasive Machining

In Hwan Lee;Seung Pyo Lee;Tae Jo Ko;Hyun Wook Kang;Dong-Woo Cho

Year: 2008 | Conference Paper |

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