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Power analysis for two-stage high resolution pipeline SAR ADC
2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)
Year: 2015 | Conference Paper |
Cited by: Papers (1)
In this paper, we provide a detailed analysis on the power consumption of two-stage pipeline successive approximation analog-to-digital converter (SAR ADC) and also show the relationship between stage resolution and the total power consumption in 65 nm technology. Thereafter, we evaluate the analysis results with designing a 15-bit pipeline SAR ADC in 65 nm technology and also a power comparison b...Show More
Two-Stage Highly Selective Receiver Front End Based on Impedance Transformation Filtering
In order to achieve blocker rejection comparable to surface acoustic wave (SAW) filters, we propose a two-stage tunable receiver front-end architecture based on impedance frequency transformation and low-noise transconductance amplifier (LNTA) circuits. The filter rejection is captured by a linear periodically varying model that includes band limitation by the LNTA output impedance and the related...Show More
Low noise linear and wideband transconductance amplifier design for current-mode frontend
2014 International Symposium on Integrated Circuits (ISIC)
Year: 2014 | Conference Paper |
Cited by: Papers (3)
A low-noise transconductance amplifier (LNTA) aimed at current-mode (Saw-less, Software-define radio) wideband receiver frontend is presented. In this application, the LNTA operates with a capacitive load to provide high linearity and sufficient Gm gain over a wide frequency band. By combination of various circuit techniques the LNTA, which is designed in 65 nm CMOS, achieves in simul...Show More
Highly linear open-loop output driver design for high speed capacitive DACs
2013 NORCHIP
Year: 2013 | Conference Paper |
Design of a high speed output driver for capacitive digital-to-analog converters (SC DACs) is presented. As the output voltage swing of those DACs is usually greater than 300 mVpp the driver is designed for large signal operation that is a challenge in terms of the DAC linearity. Two non-linearity cancellation techniques are applied to the driver circuit, the derivative superposition (DS) and the ...Show More
Blocker and image reject low-IF frontend
2013 European Conference on Circuit Theory and Design (ECCTD)
Year: 2013 | Conference Paper |
Cited by: Papers (3)
In this paper we present a design of a low-IF receiver frontend using a selective N-path filter which serves blocker rejection, image rejection, and downconversion. The filter makes use of quadrature impedance upconversion technique using multiphase clocking and can be programmed by baseband capacitance and gm-cell transconductance values to meet the low-IF criterion in various cases. Presented is...Show More
A 0.35μm CMOS 6-bit current steering DAC
Anand Narayanan;Mikael Bengtsson;Rengarajan Ragavan;Quoc-Tai Duong
2013 European Conference on Circuit Theory and Design (ECCTD)
Year: 2013 | Conference Paper |
Cited by: Papers (2)
This paper presents the design and experimental results of a high speed, low-power, thermometer coded and current steered 6-bit digital-to-analog converter (DAC). It is based on a hybrid architecture with a switched current matrix controlled by the four most significant digital bits, and a conventional 2-bit current source controlled by the two least significant bits. The DAC occupies 0.15 mm2 chi...Show More
Focused calibration for advanced RF test with embedded RF detectors
2013 European Conference on Circuit Theory and Design (ECCTD)
Year: 2013 | Conference Paper |
Cited by: Papers (2)
In this paper a technique suitable for on-chip IP3/IP2 RF test by embedded RF detectors is presented. A lack of spectral selectivity of the detectors and diverse nonlinearity of the circuit under test (CUT) impose stiff constraints on the respective test measurements for which focused calibration approach and a support by customized models of CUT is necessary. Also cancellation of second-order int...Show More
Wideband RF frontend design for flexible radio receiver
2011 International Symposium on Integrated Circuits
Year: 2011 | Conference Paper |
Cited by: Patents (1)
A wideband RF frontend for flexible radio applications is presented. A target is the performance adequate for multistandard 3G/ 4G systems operating in frequency range 0.8-6 GHz. Because of relaxed requirements on band select filters, more demands are placed on linearity while the necessary noise performance is assured. We discuss architecture with Low Noise Transconductance Amplifier (LNTA) and a...Show More
Low noise transconductance amplifier design for continuous-time ΣΔ wideband frontend
2011 20th European Conference on Circuit Theory and Design (ECCTD)
Year: 2011 | Conference Paper |
A low-noise transconductance amplifier (LNTA) aimed at continuous-time ΣΔ wideband frontend is presented. In this application, the LNTA operates with a capacitive load to provide high linearity and sufficient Gm gain over a wide frequency band. By combination of various circuit techniques the LNTA, which is designed in 65nm CMOS, achieves in simulation the noise figure less than 1.35 dB and linear...Show More
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