Contents I. Introduction
Analog to digital converter (ADC) play an important role in many broad areas including communication system, biomedical applications [1] etc. The researchers have implemented several ADC architectures depending on the necessities in different fields. ADC has different types including flash ADC, counter type, SAR ADC, pipeline ADC, sigma delta ADC, folding & interpolating ADC etc [2]. Flash ADC has higher speed among all its types [2]–[3] due to parallel architecture. However, its power consumption increases exponentially with respect to number of bits [4]–[5]. On the other hand, the SAR ADC [6] provides the feature of less chip area [7]–[8] in trade off with the speed [8] due to limitations [9]–[10] in settling time of reference voltage [11]–[12]. To address the issue of tradeoff, binary search ADC was adopted in the research area to offer the advantage of chip area & speed [13]–[14]. The binary search ADC supports the feature of better speed [15] while consuming low power [16] relatively. In comparison with flash ADC, a binary search ADC enable to support low power due to its asynchronous nature [17]. However the usage of comparator and switching network poses some critical issues in such ADCs. Particularly the usage of comparator in achieving analog to digital conversion is still the point of research in such data converters domain. The use of hybrid topology in achieving data conversion has also not extensively explored for achieving optimized speed, area and power dissipation issues. An attempt has therefore been made in the proposed work by using hybrid or two-step architectures to further save the power and chip area issue arising due to comparators while maintaining the optimization in conversion speed of ADCs. Attempt on reducing comparator count has however made earlier by A. Seyed [17], L.Ying et al. [18] and V.Geert, V.Bob [19] but limited research can be found on hybrid topology.
