A Modified DPWM Method With Minimal Line Current Ripple and Zero-Sequence Circulating Current for Two Parallel Interleaved 2L-VSIs

High-performance comprehensive optimization of line current ripple, zero-sequence circulating current (ZSCC), and switching losses is a challenge for parallel interleaved inverters. This article proposes a modified discontinuous pulse width modulation (PWM) method for two parallel interleaved two-level voltage-source inverters (2L-VSIs), which are regarded as a single 3L-VSI to optimize its vector sequence. The line current ripple is the priority optimization target to guarantee the principle of the nearest three vectors is applied in each subsector. To reduce the ZSCC and switching losses, the vector combinations with smaller changing rate of ZSCC are selected, and the phase-leg carrying the highest current is clamped. The detailed design procedure of 3L-vector sequence and how to distribute to 2L-VSIs are revealed. The quantitative performance comparison between the proposed PWM method and existing ones in terms of line current ripple, ZSCC, and switching losses are made. Experimental results confirm the effectiveness of the proposed method.

I. Introduction

Considering the capability limitation of current commercial semiconductor devices, parallel interleaved topology has been the converter of choice in the medium and high power applications due to its higher power handling, increased efficiency and reduced current ripple [1]–[3]. The topology of two parallel interleaved two-level voltage-source inverters (2L-VSIs) is shown in Fig. 1. Two inverters are usually connected with shared dc-link, thus providing a current path for zero-sequence circulating current (ZSCC). Large ZSCC will increase the stress on the semiconductor devices and cause additional system losses. Inserting the ac-side inductor such as common-mode inductor is an effective approach to suppress ZSCC peak value. However, extra passive filters will significantly increase the system volume. Therefore, many ZSCC suppression PWM methods have been proposed. Besides the issue of ZSCC, the line current ripple and switching losses are also becoming the focus of research for parallel VSIs. Fig. 1.

Topology of two parallel interleaved 2L-VSIs.