Study of wafer orientation dependence on performance and reliability of CMOS with direct-tunneling gate oxide

With the expected limitations of conventional CMOS downsizing, various new structures, such as vertical and concave MOSFETs, are under serious investigation. These new types of MOSFETs have a special feature in that the channel of the MOSFETs consists of various surfaces with different crystal orientations. With thinning of the gate oxides, the substrate orientation dependence of the oxide quality becomes a major concern, because Si-SiO/sub 2/ interface quality control becomes important in terms of suppressing the tunneling leakage current and improving TDDB reliability (Sorsch et al., 1998). This paper, for the first time, reports the surface orientation dependence of the ultra-thin gate oxide properties in the direct tunneling regime. Various characteristics of the oxide and MOSFET properties were compared by fabricating direct-tunneling gate CMOS on [100]-, [100] 4/spl deg/off, and [111]-oriented Si substrates.

Introduction

With the expected limitation in the conventional CMOS downsizing, various new structures - such as vertical and concave MOSFETs - are seriously investigated. These new types of MOSFETs have a special feature that the channel of the MOSFETs consists of various surfaces with different crystal orientation. With thinning the gate oxides, the substrate orientation dependence of the oxide quality will be a big concern, because the quality control of Si/SiO₂ interface becomes important in terms of suppressing the tunneling leakage current and improving TDDB reliability [1].