A 250 MHz-to-1.6 GHz Phase Locked Loop Design in Hybrid FinFET-Memristor Technology

There are tremendous improvements in performance of transistor in CMOS technology by scaling down its size. However, there are various challenges, such as short channel effects (SCE), that are associated with miniaturization. FinFET technology is a promising technique to overcome these issues because it offers better electrostatic control of the channel than planar CMOS transistor as the technology scales down. In this work, we have proposed a phase locked loop (PLL) design with FinFET and memristor. The resistive and capacitive (R-C) components of loop filter are replaced with memristor and memcapacitor, respectively, in order to minimize the die area and reduce power consumption. The designed PLL produces a tuning range of 0.25 - 1.60 GHz at center frequency of 1 GHz with 2.05 mW average power consumption. The voltage-controlled oscillator (VCO), which contributes majorly to the total phase noise in phase locked loop, has a phase noise -135.2 dBc/Hz at 1 MHz offset frequency. In addition, the PLL shows high reliability with wide variations in temperature.

I. Introduction

Because of the advancement in technology and demands for high packing density, high speed and low power integrated chips (ICs), it is highly desirable to scale down transistor’s channel length. This task has proven to be quite challenging in planar CMOS structure owing to the problem of short channel effects (SCE). When a transistor is properly biased with the appropriate gate-source voltage (V_GS), the electrons are able to summon the barrier and flow from the source terminal to the drain terminal. In short channel device, the application of high drain voltage tends to lower the potential barrier for electrons to flow from the source to the drain. The I_OFF current is increased, which reduces the I_ON/I_OFF ratio and causes shift in the threshold voltage (ΔV_th). In addition, the subthreshold slope (SS) is degraded and becomes difficult to switch off the transistor. This phenomenon is known as drain induced barrier lowering (DIBL). The planar MOSFETs also suffer from mismatch in V_th as a result of random dopant fluctuations [1]. However, this atomistic effect is less significant in FinFET due to its lightly doped body [2]. Over the years, FinFET technology is replacing the conventional planar structure MOSFETs because it offers better electrostatic control of the channel and suppressed short channel effects, higher I_ON/I_OFF ratio, relatively nadesi1@lsu.edu ideal subthreshold slope, low junction capacitances, lower static leakage current, high switching speed and lower switching voltage e.t.c. Double gate FinFET also has higher hole mobility than bulk FET. Nevertheless, it has higher parasitic capacitances, which causes more delay in FinFET-based circuits.