I. Introduction
Since there is increase in the demand of portable electronics, chip manufacturing industries are being forced to adopt ultralow power designs in order to conserve battery. The recent technology scaling, whereby the channel length of the transistor is reduced, has resulted in high static power. This is because of high leakage current and a phenomenon called short channel effect in MOSFETs [1]. Unlike the planar structure of MOSFET, FinFET has a vertical structure and better electrostatic control of the channel. In addition, it has reduced random dopant fluctuation, less mismatch, and higher the ratio even at super-threshold . However, the problem of high leakage power re-occurred at sub 28nm technology nodes. Tunnel field effect transistor (TFET) is a potential candidate for continuing the international technology roadmap for semiconductor (ITRS) and extending Moore's law. It can operate with low voltage (sub-0.5V), which makes it suitable for ultra-low power designs and applications [2]. When compared with thermionic-based MOSFET, tunnel field effect transistor operates based on alignment and misalignment of conduction band and valence band. The charge carriers are injected through band-to-band tunneling effects. The source and drain of TFET are usually made of different materials with different doping. This is in contrast with conventional MOSFET or FinFET where the same material is used for both source and drain. When the gate-source region of TFET is properly biased, the channel valence band aligns with the source conduction band so as to inject carriers. Some of the most intriguing features are low leakage current and low static power. It quite clear that TFET is superior in performance to MOSFET because it allows reduction in (overdrive voltage) without increase in the leakage power [3]–[5].