Modeling the Effects of SBD, HCI, and NBTI in CMOS Voltage Controlled Oscillator Design for PLL Applications

In this paper, two different structures of phase locked loop (PLL) are examined and designed in 0.13 µm n-well CMOS process technology. The two PLLs only differ in voltage-controlled oscillator (VCO): current starved and LC VCOs. Using device degradation models and equations, their performances are investigated under the combined effects of soft breakdown, hot carrier injections, and negative bias temperature instability. It is observed in the current starved VCO that the gain reduces by 33.5%, the maximum frequency decreases from 1180 MHz to 1100 MHz, and the phase noise increases from −107.6 dBc/Hz to −103.5 dBc/Hz at 1 MHz offset frequency after 6 hours of stress. The varactor degradation in LC voltage-controlled oscillator causes a decrease in the mean capacitance, resulting in increased oscillation frequency. In addition, the phase noise increases from −120 dBc/Hz to −117.2 dBc/Hz at 1 MHz frequency.

I. Introduction

One of the most widely employed circuits in the field of communication systems, computer engineering, and power electronics is Phase locked loop (PLL). Among its various applications are data and clock recovery, clock distribution, timing control, frequency synthesizer, etc. It consists of various building blocks such as phase frequency detector, charge pump, loop filter, and frequency divider circuit. With recent developments in RF applications, there is a need for designing PLL with wide tuning range, reduced settling time, low phase noise and power consumption. Over the years, the phase locked loop has been implemented in various technologies like GaAs pHEMT [1], bipolar junction transistor, and BiCMOS [2], but a fully complementary metal oxide semiconductor (CMOS) PLL design is preferred. This is because of scalability of MOS transistors, easy fabrication, high packing density, low power, and good compatibility with other nanodevices such as memristor. In addition, studies have shown that the combination of memristor and CMOS device reduces power consumption by 20 % and offers 2–3 times area improvement [3], [4].