A 6.5–12-GHz Balanced Variable-Gain Low-Noise Amplifier With Frequency-Selective Gain Equalization Technique

This article presents a wideband balanced variable-gain low-noise amplifier (VG-LNA) implemented in a 55-nm CMOS process. The proposed LNA has two cascode stages with an interstage matching transformer to constitute a fourth-order magnetically coupled resonator with two resonant peaks. The frequency-selective gain equalization technique is proposed to compensate for the gain variation of interstage dual-resonant tanks. This VG-LNA leverages a current-steering technique to realize a phase-invariant 18-dB tunable gain range with a measured input 1-dB gain compression point (IP1dB) at 9 GHz from -12.2 to -5 dBm. The LNA achieves a power gain of 20.2 dB with ±0.5-dB gain variation and a noise figure (NF) of 3.26 dB from 6.5 to 12 GHz. Due to the lumped Lange couplers, the input and output matching are both better than -14 dB. This chip occupies 1.44 × 0.68 mm² area excluding pads and consumes 75 mW.

I. Introduction

Wideband receivers have attracted tremendous attention for high communication data rates. Especially, the broadband satellite communication working on X-band or C-band have motivated extensive studies on the wideband transceiver for wireless applications. As a critical component of the receiver, low-noise amplifier (LNA) determines the performance of the wireless system, especially the dynamic range and sensitivity. Due to the high-electron-mobility characteristics, devices in the III–V semiconductor process produce less noise than the silicon process. However, the development of advanced CMOS processes provides a high-integration low-cost solution for system-on-a-chip (SoC) applications. Different techniques have been proposed to effectively advance individual aspect of silicon-based LNA performance, such as input matching, noise figure (NF), or power gain [1]–[6]. However, it is very challenging to address all the key aspects simultaneously due to design tradeoffs, such as wide bandwidth, NF, gain flatness, linearity, and input matching.