Abstract:
Some of the critical issues of wafer level chip scale package (WLCSP) are discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the im...Show MoreMetadata
First Page of the Article
Abstract:
Some of the critical issues of wafer level chip scale package (WLCSP) are discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the important parameters such as wafer-level redistribution, wafer bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layers on the solder joint reliability of WLCSP on printed circuit boards (PCB) through creep responses such as deformation, hysteresis loops, and stress and strain are presented. Only solder-bumped WLCSPs with pad-redistribution are considered in this study.
Published in: Twenty Sixth IEEE/CPMT International Electronics Manufacturing Technology Symposium (Cat. No.00CH37146)
Date of Conference: 03-03 October 2000
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-6482-1
Print ISSN: 1089-8190
First Page of the Article
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