Wafer level CSP using low cost electroless redistribution layer

A driving force to achieve increased speed and performance along with higher I/O count is the Flip Chip (FC) Technology which has therefore an high level of importance for a variety of applications. A breakthrough, however, will be the use of flip chip due to cost reduction. For this aim it is essential to use low cost bumping techniques. However, to provide FC technologies also for devices with high I/O count and high pin density applications like Microcontrollers, RAMBUS devices, etc.... it is necessary to redistribute the historically peripheral bond pads with ultra fine pad pitch into a wafer level CSP. This paper describes a low cost electroless Ni/Au Under Bump Metallization (UBM) and a wafer level redistribution process based on electroless copper circuitization. It includes the use of a novel plasma enhanced chemical vapour deposition (PECVD) process to deposit a bifunctional nanolayer acting as an adhesion promotor and as a catalyst for electroless copper deposition. The described techniques are suitable for all wafer passivation types, which are used in industry today. The complete redistribution process is based on batch processing and less masking and photoimaging steps. By using the electroless Nickel process and wafer level stencil solder printing the process is highly cost efficient and has large volume manufacturing capability. Results and also reliability measurements will be presented. Finally a roadmap regarding the implementation of this process into backend high volume production is shown.