Achieving Minimal PDN Impedance, SSN and Jitter on PCB with Embedded Capacitance Material

In this paper, the imperativeness of low power distribution network (PDN) impedance on printed circuit board (PCB) with high frequency signals operating at hundreds of Mega-Hz range and the impact of embedded capacitance material (ECM) in minimizing wideband PDN impedance are discussed. The study to compare the performance of PCB with ECM versus conventional dielectric FR4 material was conducted with post-layout power integrity simulation using Keysight ADS on the power net of interest, followed by measurement of PDN impedance and simultaneous switching noise (SSN) using network analyzer (VNA) and oscilloscope respectively on prototype PCB. Lastly, eye diagram and jitter of the high frequency clock signal on the PCB are observed. The correlated simulation and measurement results are presented and discussed in the later section of this paper.

I. Introduction to PDN impedance and embedded capacitance material

It is important to keep power distribution network (PDN) impedance on printed circuit board (PCB) low to minimize the switching noise contributed by transient current in any ICs connected to the power rail. With reference to (1) [1] , transient current in IC interacts with PDN impedance and generates simultaneous switching noise (SSN). This noise is induced to the power rail and could contribute to signal and power integrity (SI/PI), jitter and electromagnetic interference (EMI) issue.

$$\begin{equation*}V_{pp,Noise} = I_{tr} \times Z_{PDN}\tag{1}\end{equation*}$$

V _pp,Noise = simultaneous switching noise on power rail

I _tr = transient current in IC

Z _PDN = PDN impedance