Design of a low-jitter wideband frequency synthesizer for 802.11ad wireless OFDM systems using a frequency sixtupler

The rms timing jitter of a phase-locked loop (PLL) is calculated and minimized analytically from the VCO phase noise and the in-band phase noise plateau with and without digital baseband correction in an OFDM system. Subsequently, we present an integrated wideband frequency synthesizer in a 130 nm SiGe BiCMOS technology. An 8.7 GHz-11.8 GHz PLL using only one VCO is followed by a frequency sixtupler composed of a tripler and a doubler. The measured phase noise at 1 MHz offset from the 10 GHz PLL output frequency is below -108 dBc/Hz. For a 60 GHz OFDM system, this corresponds to an rms phase error of 1.5° and a PLL rms jitter of 70 fs after common phase error correction. The synthesizer chip occupies a chip area of 3.6 mm² and draws 144 mA from a 3.3 V supply.

I. Introduction

Millimeter-wave frequency synthesizers with a low phase noise are needed, e.g., in wideband transceivers in the 60 GHz band (57-64 GHz), in W-band (75-110 GHz) imaging systems, in point-to-point communication systems in the E-band (71-76 GHz, 81-86 GHz), 100-Gbps Ethernet, and in 120 GHz wireless transceivers. Voltage-controlled oscillators (VCO) with a sufficient tuning range are difficult to realize at such frequencies. As an alternative, lower-frequency VCOs followed by frequency multipliers can be used. Silicon-based frequency triplers with low phase noise have been demonstrated for output frequencies as high as 100 GHz [1]. As an alternative, a push-push doubler can be used to double the frequency and delivers a single-ended output signal [2]. However, a differential output is often preferred for driving a differential mixer, a differential antenna or another frequency doubler. A Gilbert mixer can be used as a differential frequency doubler by connecting LO and RF port to the same input [3].