Dynamic Selection and Estimation of the Digital Predistorter Parameters for Power Amplifier Linearization

This paper presents a new technique that dynamically estimates and updates the coefficients of a digital predistorter (DPD) for power amplifier (PA) linearization. The proposed technique is dynamic in the sense of estimating, at every iteration of the coefficient's update, only the minimum necessary parameters according to a criterion based on the residual estimation error. At the first step, the original basis functions defining the DPD in the forward path are orthonormalized for DPD adaptation in the feedback path by means of a precalculated principal component analysis (PCA) transformation. The robustness and reliability of the precalculated PCA transformation (i.e., PCA transformation matrix obtained off line and only once) is tested and verified. Then, at the second step, a properly modified partial least squares (PLS) method, named dynamic partial least squares (DPLS), is applied to obtain the minimum and most relevant transformed components required for updating the coefficients of the DPD linearizer. The combination of the PCA transformation with the DPLS extraction of components is equivalent to a canonical correlation analysis (CCA) updating solution, which is optimum in the sense of generating components with maximum correlation (instead of maximum covariance as in the case of the DPLS extraction alone). The proposed dynamic extraction technique is evaluated and compared in terms of computational cost and performance with the commonly used QR decomposition approach for solving the least squares (LS) problem. Experimental results show that the proposed method (i.e., combining PCA with DPLS) drastically reduces the amount of DPD coefficients to be estimated while maintaining the same linearization performance.

I. Introduction

Digital predistortion (DPD) linearization can overcome or at least mitigate the efficiency versus linearity tradeoff in power amplifiers (PAs). In order to avoid wasting excessive power resources when handling high peak-to-average power ratio (PAPR) signals, high-efficient amplification architectures based on dynamic load or dynamic supply modulation have been adopted. Some of the most popular solutions proposed in the literature (and also adopted by the industry in some cases) include: envelope tracking PAs [1], Doherty PAs [2], load-modulated balanced amplifiers (LMBAs) [3], and LINC or outphasing PAs [4]. In either case, these highly efficient topologies require the use of linearization techniques to guarantee the linearity levels specified in the communication standards.