Loading [MathJax]/extensions/MathZoom.js
Pere L. Gilabert - IEEE Xplore Author Profile

Showing 1-25 of 72 results

Filter Results

Show

Results

This paper offers a thorough comparison of two families of digital predistortion (DPD) behavioral models used for the linearization of high-efficiency dual-input wideband power amplifiers. Specifically, N-stage cascaded (CC) models are compared with artificial neural networks (ANNs) models in terms of linearization performance and computational complexity. The DPD models are designed balancing the...Show More
This paper explores the benefits of utilizing multistage cascaded (CC) behavioral models for digital predistortion (DPD) linearization of wideband high-efficiency power amplifiers (PAs). To reduce the computational complexity of these multistage CC behavioral models, a model-order reduction technique based on a greedy algorithm is proposed. The advantages of employing CC DPD models with gradient d...Show More
This paper presents a power amplifier architecture based on outphasing. Both active devices are operated as current sources loaded by a single-ended load. The combination of phase and amplitude control allows for maintaining a constant voltage and, therefore, high efficiency on the devices' output. Output series compensation reactances reduce the imaginary part of the modulated load and improve ef...Show More
This paper discusses the best identification approach to estimate the parameters of cascaded (CC) behavioral models for digital predistortion (DPD) linearization of high efficient wideband power amplifiers. The commonly used least squares (LS) identification method is compared to the proposed gradient descent (GD) -based optimization approach. Experimental results considering a 5G new radio (NR) t...Show More
This article presents a scalable digital predistortion (DPD) linearizer for handset power amplifiers (PAs) with nonflat frequency response and assuming a 5G scenario with dynamic resource blocks (RBs) reallocation. The scalable DPD model is designed to be both bandwidth and frequency-dependent, including some design constraints targeting a resource-efficient hardware implementation. In order to ex...Show More
This paper presents shaping and linearization techniques to trade-off linearity and power efficiency in a dual-input pseudo-Doherty load-modulated balanced amplifier (PD-LMBA). The proposed shaping function is defined to operate in the frequency domain and it is oriented at exploiting the dual-input architecture of the PD-LMBA to either enhance linearity or power efficiency. In addition, since the...Show More
This paper presents an automated process for generating computationally efficient radiofrequency (RF) power amplifier (PA) behavioural models that can be used for digital-predistortion (DPD) linearization. The implementation of the DPD behavioral model is based on the personal computer (PC) architecture including recent graphical process units (GPUs) with compute unified device architecture (CUDA)...Show More
This paper presents a low-complexity open-loop digital linearization system for handset applications with non-flat frequency response when considering a 5G new radio dynamic bandwidth re-allocation scenario. The proposed digital predistorter (DPD) is scalable with the signal bandwidth by simply activating or deactivating basis kernels, without re-training nor re-assigning the model coefficients. T...Show More
This paper proposes the method of extracting a shaping function for operating a family of Dual Input Power Amplifiers operating with modulated signals such as OFDM-based 5G new radio (NR) signals. The shaping function describing the drive profile for each input was implemented using a Look-Up Table (LUT) approach. This table can be constructed from the previously measured PA data to target various...Show More
This paper presents two linearization strategies for a custom-designed wideband push-pull (PP) power amplifier (PA) for wired communication applications such as, for example, cable TV. Two digital predistortion (DPD) behavioral models are proposed to meet the in-band and out-of-band linearity requirements when efficiently amplifying wideband DOCSIS signals with high fractional bandwidth (FBW). A r...Show More
This paper presents a novel linearization method to compensate for load-mismatched power amplifiers in 5G new radio mobile terminals. The proposed digital predistortion (DPD) approach is based on a frequency-dependent memoryless polynomial behavioral model that allows meeting the linearity specifications under dynamic resource block (RB) allocation when considering narrowband signals. The advantag...Show More
This article focuses on the implementation of a linearization system for envelope tracking (ET) power amplifiers (PAs) in field-programmable gate array (FPGA). The ET PA linearization system includes a slew-rate reduction envelope generator, a RF leakage cancellation system in the supply envelope path and a baseband $I - Q$ digital predistorter (DPD). This work targets the implementation of an E...Show More
This article presents a low-complexity linearization method to compensate for multisource nonlinear distortion in wideband envelope tracking (ET) power amplifiers (PAs) for 5G new radio (NR) mobile terminals. The proposed linearization approach consists in an envelope leakage cancellation (ELC) system operating in the dynamic supply path and a 2-D digital predistortion (2-D-DPD) linearizer acting ...Show More
In 5G and beyond radios, the increased bandwidth, the fast-changing waveform scenarios, and the operation of large array multiple-input multiple-output (MIMO) transmitter architectures have challenged both the polynomial and the artificial neural network (ANN) MIMO adaptive digital predistortion (DPD) schemes. This article proposes training data selection methods and dimensionality reduction techn...Show More
This paper focuses on the FPGA implementation of a slew-rate reduction (SR) shaping function for envelope tracking (ET) power amplifiers (PAs). The SR envelope has been proved effective to trade-off power efficiency and linearity in ET PA systems where the envelope tracking modulator (ETM) is bandwidth limited. However, the implementation issues need to be addressed when targeting high clock rates...Show More
This paper presents a new linearization method to compensate for the unwanted RF leakage that appears at the ouput of envelope tracking modulators (ETMs) when operating envelope tracking (ET) power amplifiers (PAs) with wideband signals. This RF leakage is combined in the ETM with the dy-namic supply signal and generates unwanted nonlinear distortion at the RF output of the ET PA. A leakage cancel...Show More
This article proposes a methodology to ensure linear amplification of a load modulated balanced amplifier (LMBA) while keeping the power efficiency as high as possible over a frequency band ranging from 1.8 to 2.4 GHz and where the transmitted signals can present different bandwidth (BW) configurations. The proposed reconfigurable linearization methodology consists of, in a first step, tuning some...Show More
This paper presents a scalable look-up table (LUT) architecture for implementing digital predistortion (DPD) linearizers in a field programmable gate array (FPGA) by using the high-level synthesis (HLS) software. This architecture can be used in most memory-based DPD behavioral models whose basis functions can be expressed as a combination of basic predistortion cells (BPCs). The advantages of the...Show More
The artificial neural networks (ANN) are gaining momentum in the digital predistorters (DPD) thanks to their inherently good approximation capabilities. Under strong or complex power amplifier nonlinearities, the size of the ANN can increase and lead to long training periods which are unaffordable in fast-changing waveform scenarios like those proposed for 5G or 6G. In this work we combine the ort...Show More
This letter proposes a mesh-selecting (MeS) method for complex-valued signals oriented at significantly reducing the training data required to extract the parameters of mathematical models for characterizing the nonlinear behavior of power amplifiers or digital predistortion linearizers. Experimental results will show the advantages of the proposed MeS method when properly combined with dimensiona...Show More
Digital predistortion (DPD) is the linearization technique most often used to cope with the inherent tradeoff between linearity and efficiency in power amplifiers (PAs). Adaptation is needed to optimize DPD performance. This article reviews strategies for estimating the parameters controlling the DPD linearizer.Show More
This paper evaluates the effect of the phase shift between the two control signals in a dual-input load modulated balanced amplifier (LMBA). While the drain efficiency of the LMBA is not significantly affected by the phase shift between the control signals, the LMBA linearity instead can be significantly degraded if the phase shift parameter is not properly chosen. Therefore, we can predict the op...Show More
This paper presents a holistic approach to design and linearize a wideband outphasing power amplifier (PA) to efficiently amplify a 200 MHz bandwidth (BW) signal compliant with the Data Over Cable Service Interface Specification (DOCSIS) standard. The proposed outphasing PA, based on a load insensitive GaN HEMT class-E topology, was designed to face the trade-off between the output power control r...Show More
This paper presents a new technique that dynamically estimates and updates the coefficients of a digital predistorter (DPD) for power amplifier (PA) linearization. The proposed technique is dynamic in the sense of estimating, at every iteration of the coefficient's update, only the minimum necessary parameters according to a criterion based on the residual estimation error. At the first step, the ...Show More
In this paper, a new method for dynamically estimating and updating the coefficients of a digital predistortion (DPD) linearizer is presented. By means of the partial least squares (PLS) algorithm, the basis matrix used in the DPD estimation/adaptation is dynamically updated at every iteration to minimize the linearization error. Moreover, only the minimum necessary DPD coefficients being required...Show More