Loading [MathJax]/extensions/MathMenu.js
The Quest of the Ideal Error Detecting Architecture: The GRAAL Architecture | IEEE Journals & Magazine | IEEE Xplore

The Quest of the Ideal Error Detecting Architecture: The GRAAL Architecture


Abstract:

Silicon-based CMOS technologies are fast approaching their ultimate limits. By approaching these limits, fabrication yield, reliability, and power densities, worsen stead...Show More

Abstract:

Silicon-based CMOS technologies are fast approaching their ultimate limits. By approaching these limits, fabrication yield, reliability, and power densities, worsen steadily making further nanometric scaling increasingly difficult. These problems would become showstoppers in ultimate-CMOS and post-CMOS technologies, unless efficient fault-mitigation and low-power approaches are developed to maintain acceptable levels of yield, reliability, and power densities. This paper describes the GRAAL architecture, which improves significantly the fault detection efficiency, cost, and timing constraints of the double-sampling approach, providing this way an efficient scheme for solving the issues induced by aggressive technology scaling in the era of ultimate-CMOS and post-CMOS technologies.
Published in: IEEE Transactions on Sustainable Computing ( Volume: 6, Issue: 3, 01 July-Sept. 2021)
Page(s): 493 - 506
Date of Publication: 31 October 2018

ISSN Information:

References is not available for this document.

1 Introduction

Aggressive technology scaling has dramatic impact on: (1) process, voltage, and temperature (PVT) variations; (2) circuit aging and wearout induced by failure mechanisms such as NBTI, HCI; (3) clock skews; (4) sensitivity to EMI (e.g., cross-talk and ground bounce); (5) sensitivity to radiation-induced single-event effects (SEUs, SETs); and (6) power dissipation and thermal constraints. The resulting high defect levels, heterogeneous behavior of identical circuit nodes, circuit degradation over time, and integrated circuits complexity, affect adversely fabrication yield, reliability, and circuit lifespan.

Select All
1.
A. Drake, R. Senger, H. Deogun et al., "A distributed critical-path timing monitor for a 65nm high-performance microprocessor", Proc. IEEE Int. Solid-State Circuits Conf.. Dig. Tech. Papers, pp. 398-399, Feb. 2007.
2.
T. Burd, T. Pering, A. Stratakos and R. Brodersen, "A dynamic voltage scaled microprocessor system", IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1571-1580, Nov. 2000.
3.
M. Nakai, S. Akui, K. Seno et al., "Dynamic voltage and frequency management for a low-power embedded microprocessor", IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 28-35, Jan. 2005.
4.
K. Nowka et al., "A 32-bit power PC system- on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling", IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1441-1447, Nov. 2002.
5.
M. Nicolaidis, "Time redundancy based soft-error tolerant circuits to rescue very deep submicron", Proc. 17th IEEE VLSI Test Symp., pp. 86-94, Apr. 1999.
6.
M. Nicolaidis, "Circuit logique protégé contre des perturbations transitoires", Mar. 8, 2000.
7.
L. Anghel and M. Nicolaidis, "Cost reduction and evaluation of a temporary faults detecting technique", Proc. Des. Autom. Test Europe Conf., pp. 591-598, Mar. 2000.
8.
D. Ernst et al., "Razor: A low-power pipeline based on circuit-level timing speculation", Proc. 36th Intl. Symp. Microarchitecture, pp. 7-18, Dec. 2003.
9.
D. Ernst et al., "Razor: Circuit-level correction of timing errors for low-power operation", IEEE Micro, vol. 24, no. 6, pp. 10-20, Nov./Dec. 2003.
10.
S. Das et al., "A self-tuning DVS processor using delay-error detection and correction", Proc. IEEE Symp. VLSI Circuits, pp. 258-261, Jun. 2005.
11.
P. Franco and E. J. McCluskey, "On-line delay testing of digital circuits", Proc. 12th IEEE VLSI Test Symp., pp. 167-173, Apr. 1994.
12.
C. Metra, M. Favalli and B. Ricco, "On-line detection of logic errors due to crosstalk delay and transient faults", Proc. Int. Test Conf., pp. 524-533, Oct. 18-23, 1998.
13.
S. Das et al., "RazorII: In situ error detection and correction for PVT and SER tolerance", IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 32-48, Jan. 2009.
14.
M. Nicolaidis, "GRAAL: A new fault-tolerant design paradigm for mitigating the flaws of deep-nanometric technologies", Proc. IEEE Int. Test Conf., pp. 1-10, Oct. 23-25, 2007.
15.
H. Yu, M. Nicolaidis, L. Anghel and N. Zergainoh, "Efficient fault detection architecture design of latch-based low power DSP/MCU processor", Proc. 16th IEEE Eur. Test Symp., pp. 93-98, Mai 2011.
16.
17.
J.-L. Nagel, C. Arm, A. Corbaz, M. Morgan, V. Moser and P. Volet, "The icyflex2 processor architecture".
18.
"Design compiler user guide", Dec. 1, 2015.
19.
"PrimeTime user guide", Oct. 19, 2012.
20.
"VCS®/VCSi™ user guide", Nov. 2013.
21.
D. Rossi, M. Omaña and C. Metra, "Transient fault and soft error on-die monitoring scheme", IEEE Int. Symp. Defect Fault Tolerance VLSI Syst., pp. 391-398, Oct. 6-8, 2010.
22.
M Saliva, F Cacho, V Huard, X Federspiel, D. Angot, A. Benhassian, et al., "Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI", Proc. Des. Autom. Test Europe Conf., pp. 441-446, Mar. 09-13, 2015.
23.
M. Nicolaidis, " Double-sampling design paradigm – A compendium of architectures ", IEEE Trans. Device Mater. Rel., vol. 15, no. 1, pp. 10-23, Mar. 2015.
24.
A. Tiwari, S. R. Sarangi and J. Torrellas, "ReCycle: Pipeline adaptation to tolerate process variation", Proc. Int. Symp. Comput. Archit., pp. 323-334, Jun. 9-13, 2007.
25.
B. Greskamp, L. Wan, U. R. Karpuzcu, J. J. Cook, J. Torrellas, D. Chen, et al., "Blueshift: Designing processors for timing speculation from the ground up", Proc. IEEE Int. Symp. High Perform. Comput. Archit., pp. 213-224, Feb. 14-18, 2009.

References

References is not available for this document.