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The Quest of the Ideal Error Detecting Architecture: The GRAAL Architecture | IEEE Journals & Magazine | IEEE Xplore

The Quest of the Ideal Error Detecting Architecture: The GRAAL Architecture


Abstract:

Silicon-based CMOS technologies are fast approaching their ultimate limits. By approaching these limits, fabrication yield, reliability, and power densities, worsen stead...Show More

Abstract:

Silicon-based CMOS technologies are fast approaching their ultimate limits. By approaching these limits, fabrication yield, reliability, and power densities, worsen steadily making further nanometric scaling increasingly difficult. These problems would become showstoppers in ultimate-CMOS and post-CMOS technologies, unless efficient fault-mitigation and low-power approaches are developed to maintain acceptable levels of yield, reliability, and power densities. This paper describes the GRAAL architecture, which improves significantly the fault detection efficiency, cost, and timing constraints of the double-sampling approach, providing this way an efficient scheme for solving the issues induced by aggressive technology scaling in the era of ultimate-CMOS and post-CMOS technologies.
Published in: IEEE Transactions on Sustainable Computing ( Volume: 6, Issue: 3, 01 July-Sept. 2021)
Page(s): 493 - 506
Date of Publication: 31 October 2018

ISSN Information:

Author image of Michael Dimopoulos
TIMA Laboratory, Grenoble, France
Michael Dimopoulos received the diploma degree in physics, the master's degree in electronics, and the PhD degree in computer science from the Aristotle University of Thessaloniki, Greece, in 1993, 1996, and 2004, respectively. Currently, he is a Design-For-Test engineer at Dialog Semiconductor GmbH in the Munich area, Germany. Prior to that from Nov. 2011 to May 2016, he was a post-doctoral research associate at TIMA Lab...Show More
Michael Dimopoulos received the diploma degree in physics, the master's degree in electronics, and the PhD degree in computer science from the Aristotle University of Thessaloniki, Greece, in 1993, 1996, and 2004, respectively. Currently, he is a Design-For-Test engineer at Dialog Semiconductor GmbH in the Munich area, Germany. Prior to that from Nov. 2011 to May 2016, he was a post-doctoral research associate at TIMA Lab...View more
Author image of Michael Nicolaidis
TIMA Laboratory, Grenoble, France
Michael Nicolaidis is research director at CNRS and a member of TIMA Lab. His research interests include design for test, design for yield, design for reliability, and design for low power. He authored more than 20 patents. He has more that 240 cited publications and more than 7,500 citations. He authored one book and edited two books and several journal special issues. He received four Best Paper Awards at DATE & VTS. He...Show More
Michael Nicolaidis is research director at CNRS and a member of TIMA Lab. His research interests include design for test, design for yield, design for reliability, and design for low power. He authored more than 20 patents. He has more that 240 cited publications and more than 7,500 citations. He authored one book and edited two books and several journal special issues. He received four Best Paper Awards at DATE & VTS. He...View more

1 Introduction

Aggressive technology scaling has dramatic impact on: (1) process, voltage, and temperature (PVT) variations; (2) circuit aging and wearout induced by failure mechanisms such as NBTI, HCI; (3) clock skews; (4) sensitivity to EMI (e.g., cross-talk and ground bounce); (5) sensitivity to radiation-induced single-event effects (SEUs, SETs); and (6) power dissipation and thermal constraints. The resulting high defect levels, heterogeneous behavior of identical circuit nodes, circuit degradation over time, and integrated circuits complexity, affect adversely fabrication yield, reliability, and circuit lifespan.

Author image of Michael Dimopoulos
TIMA Laboratory, Grenoble, France
Michael Dimopoulos received the diploma degree in physics, the master's degree in electronics, and the PhD degree in computer science from the Aristotle University of Thessaloniki, Greece, in 1993, 1996, and 2004, respectively. Currently, he is a Design-For-Test engineer at Dialog Semiconductor GmbH in the Munich area, Germany. Prior to that from Nov. 2011 to May 2016, he was a post-doctoral research associate at TIMA Laboratory, Grenoble, France. He served as a lecturer (Adjunct) at the Department of Informatics, Aristotle University of Thessaloniki, Greece, from 2004 to 2011. From Oct. 2008 to Feb. 2011, he was an assistant professor (adjunct) with the Department of Electronics, Alexander Technological Educational Institute of Thessaloniki, Greece. His research interests include VLSI testing, DFT, fault tolerance, reliable design, timing, and power optimization. He serves as member of the editorial board of the Simulation Modeling Practice and Theory (SIMPAT) journal. He is a member of the IEEE.
Michael Dimopoulos received the diploma degree in physics, the master's degree in electronics, and the PhD degree in computer science from the Aristotle University of Thessaloniki, Greece, in 1993, 1996, and 2004, respectively. Currently, he is a Design-For-Test engineer at Dialog Semiconductor GmbH in the Munich area, Germany. Prior to that from Nov. 2011 to May 2016, he was a post-doctoral research associate at TIMA Laboratory, Grenoble, France. He served as a lecturer (Adjunct) at the Department of Informatics, Aristotle University of Thessaloniki, Greece, from 2004 to 2011. From Oct. 2008 to Feb. 2011, he was an assistant professor (adjunct) with the Department of Electronics, Alexander Technological Educational Institute of Thessaloniki, Greece. His research interests include VLSI testing, DFT, fault tolerance, reliable design, timing, and power optimization. He serves as member of the editorial board of the Simulation Modeling Practice and Theory (SIMPAT) journal. He is a member of the IEEE.View more
Author image of Michael Nicolaidis
TIMA Laboratory, Grenoble, France
Michael Nicolaidis is research director at CNRS and a member of TIMA Lab. His research interests include design for test, design for yield, design for reliability, and design for low power. He authored more than 20 patents. He has more that 240 cited publications and more than 7,500 citations. He authored one book and edited two books and several journal special issues. He received four Best Paper Awards at DATE & VTS. He was plenary keynote speaker in several international conferences. One of his papers was selected among the most influential papers of the 10 years of DATE. He is an IEEE senior member and Golden Core member of the IEEE Computer Society. He is a member of the editorial board of IEEE Design & Test of Computers; and the steering committees: VTS member and ITC past member. He is past chair of the Test Technology Technical Council of the IEEE Computer Society. He is founder of iRoC Technologies.
Michael Nicolaidis is research director at CNRS and a member of TIMA Lab. His research interests include design for test, design for yield, design for reliability, and design for low power. He authored more than 20 patents. He has more that 240 cited publications and more than 7,500 citations. He authored one book and edited two books and several journal special issues. He received four Best Paper Awards at DATE & VTS. He was plenary keynote speaker in several international conferences. One of his papers was selected among the most influential papers of the 10 years of DATE. He is an IEEE senior member and Golden Core member of the IEEE Computer Society. He is a member of the editorial board of IEEE Design & Test of Computers; and the steering committees: VTS member and ITC past member. He is past chair of the Test Technology Technical Council of the IEEE Computer Society. He is founder of iRoC Technologies.View more

References

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