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The Quest of the Ideal Error Detecting Architecture: The GRAAL Architecture | IEEE Journals & Magazine | IEEE Xplore

The Quest of the Ideal Error Detecting Architecture: The GRAAL Architecture


Abstract:

Silicon-based CMOS technologies are fast approaching their ultimate limits. By approaching these limits, fabrication yield, reliability, and power densities, worsen stead...Show More

Abstract:

Silicon-based CMOS technologies are fast approaching their ultimate limits. By approaching these limits, fabrication yield, reliability, and power densities, worsen steadily making further nanometric scaling increasingly difficult. These problems would become showstoppers in ultimate-CMOS and post-CMOS technologies, unless efficient fault-mitigation and low-power approaches are developed to maintain acceptable levels of yield, reliability, and power densities. This paper describes the GRAAL architecture, which improves significantly the fault detection efficiency, cost, and timing constraints of the double-sampling approach, providing this way an efficient scheme for solving the issues induced by aggressive technology scaling in the era of ultimate-CMOS and post-CMOS technologies.
Published in: IEEE Transactions on Sustainable Computing ( Volume: 6, Issue: 3, 01 July-Sept. 2021)
Page(s): 493 - 506
Date of Publication: 31 October 2018

ISSN Information:


1 Introduction

Aggressive technology scaling has dramatic impact on: (1) process, voltage, and temperature (PVT) variations; (2) circuit aging and wearout induced by failure mechanisms such as NBTI, HCI; (3) clock skews; (4) sensitivity to EMI (e.g., cross-talk and ground bounce); (5) sensitivity to radiation-induced single-event effects (SEUs, SETs); and (6) power dissipation and thermal constraints. The resulting high defect levels, heterogeneous behavior of identical circuit nodes, circuit degradation over time, and integrated circuits complexity, affect adversely fabrication yield, reliability, and circuit lifespan.

References

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