Abstract:
In this work, five methods for measuring the thickness of ultra-thin gate oxide layers in MOS structures were compared experimentally on n/sup +/ poly-SiO/sub 2/-p-Si str...Show MoreMetadata
Abstract:
In this work, five methods for measuring the thickness of ultra-thin gate oxide layers in MOS structures were compared experimentally on n/sup +/ poly-SiO/sub 2/-p-Si structures. Three methods are based on electrical capacitance-voltage (C-V) and current-voltage (I-V) data and the other two methods are HRTEM and optical measurement. MOS capacitors with oxide thickness in the range 17-55 /spl Aring/ have been used in this study. We found that thickness extracted using QM C-V and HRTEM agree within 1.0 /spl Aring/ over the whole thickness range when a dielectric constant of 3.9 was used. Comparison between thickness extracted using quantum interference (QI) I-V technique and optical measurement were also within 1.0 /spl Aring/ for thickness 31-47 /spl Aring/. However, optical oxide thickness was consistently lower than the TEM thickness by about 2 /spl Aring/ over the thickness range under consideration. Both optical measurement and QM C-V modeling yield the same thickness as the nominal oxide thickness increases (>50 /spl Aring/).
Published in: IEEE Transactions on Electron Devices ( Volume: 47, Issue: 7, July 2000)
DOI: 10.1109/16.848276
Citations are not available for this document.
Cites in Papers - |
Cites in Papers - IEEE (13)
Select All
1.
Gaspard Hiblot, "Bulk FinFET EOT Extraction from Accumulation Capacitance Measurements", IEEE Transactions on Electron Devices, vol.65, no.3, pp.874-880, 2018.
2.
Atsushi Hiraiwa, Akio Shima, Dai Ishikawa, "Completely Quantum–Mechanical Extraction of Equivalent Oxide Thickness of PMOS Gate Insulator", IEEE Transactions on Electron Devices, vol.58, no.3, pp.650-657, 2011.
3.
Ernest Y. Wu, Jordi Sune, "On Voltage Acceleration Models of Time to Breakdown—Part I: Experimental and Analysis Methodologies", IEEE Transactions on Electron Devices, vol.56, no.7, pp.1433-1441, 2009.
4.
Chang Yong Kang, Paul D. Kirsch, Byoung Hun Lee, Hsing-Huang Tseng, Rajarao Jammy, "Reliability of La-Doped Hf-Based Dielectrics nMOSFETs", IEEE Transactions on Device and Materials Reliability, vol.9, no.2, pp.171-179, 2009.
5.
Ahmad Ehteshamul Islam, Vrajesh D. Maheta, Hitesh Das, Souvik Mahapatra, Muhammad Ashraful Alam, "Mobility degradation due to interface traps in plasma oxynitride PMOS devices", 2008 IEEE International Reliability Physics Symposium, pp.87-96, 2008.
6.
P. Palestri, N. Barin, D. Brunel, C. Busseret, A. Campera, P. A. Childs, F. Driussi, C. Fiegna, G. Fiori, R. Gusmeroli, G. Iannaccone, M. Karner, H. Kosina, A. L. Lacaita, E. Langer, B. Majkusiak, C. Monzio Compagnoni, A. Poncet, E. Sangiorgi, L. Selmi, A. S. Spinelli, J. Walczak, "Comparison of Modeling Approaches for the Capacitance–Voltage and Current–Voltage Characteristics of Advanced Gate Stacks", IEEE Transactions on Electron Devices, vol.54, no.1, pp.106-114, 2007.
7.
F. Li, L.F. Register, M.M. Hasan, S.K. Banerjee, "A Program for Device Model Parameter Extraction from Gate Capacitance and Current of UltrathinhboxSiO_2and High-kappaGate Stacks", IEEE Transactions on Electron Devices, vol.53, no.9, pp.2118-2127, 2006.
8.
A.E. Islam, A. Haque, "Accumulation gate capacitance of MOS devices with ultrathin high-/spl kappa/ gate dielectrics: modeling and characterization", IEEE Transactions on Electron Devices, vol.53, no.6, pp.1364-1372, 2006.
9.
A. Teramoto, R. Kuroda, M. Komura, K. Watanabe, S. Sugawa, T. Ohmi, "Capacitance-Voltage measurement method for ultrathin gate dielectrics using LC resonance circuit", IEEE Transactions on Semiconductor Manufacturing, vol.19, no.1, pp.43-49, 2006.
10.
Fei Li, S. Mudanai, L.F. Register, S.K. Banerjee, "A physically based compact gate C-V model for ultrathin (EOT /spl sim/1 nm and below) gate dielectric MOS devices", IEEE Transactions on Electron Devices, vol.52, no.6, pp.1148-1158, 2005.
11.
A. Teramoto, M. Komura, R. Kuroda, K. Watanabe, S. Sugawa, T. Ohmi, "EOT measurement for ultra-thin gate dielectrics using LC resonance circuit [MOS devices]", Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005., pp.223-227, 2005.
12.
S. Kar, "Extraction of the capacitance of ultrathin high-K gate dielectrics", IEEE Transactions on Electron Devices, vol.50, no.10, pp.2112-2119, 2003.
13.
R.J. Carter, E. Cartier, M. Caymax, S. De Gendt, Degraevel R, G. Groeseneken, M. Heyns, T. Kauerauf, A. Kerber, S. Kubicek, G. Lujan, L. Pantisano, W. Tsai, E. Young, "Electrical characterisation of high-k materials prepared by atomic layer CVD", Extended Abstracts of International Workshop on Gate Insulator. IWGI 2001 (IEEE Cat. No.01EX537), pp.94-99, 2001.
Cites in Papers - Other Publishers (14)
1.
"Isotope analysis of diamond-surface passivation effect of high-temperature H2O-grown atomic layer deposition-Al2O3 films", Journal of Applied Physics, vol.117, no.21, pp.215304, 2015.
2.
Samares Kar, "MOSFET: Basics, Characteristics, and Characterization", High Permittivity Gate Dielectric Materials, vol.43, pp.47, 2013.
3.
Weitao Cheng, Akinobu Teramoto, Tadahiro Ohmi, "Experimental demonstration and analysis of high performance and low 1/f noise Tri-gate MOSFETs by optimizing device structure", Microelectronic Engineering, vol.86, no.7-9, pp.1786, 2009.
4.
Alvin W. Strong, Ernest Y. Wu, Rolf-Peter Vollertsen, Jordi Sune, Giuseppe La Rosa, Timothy D. Sullivan, Stewart E. Rauch, "Dielectric Characterization and Reliability Methodology" in Reliability Wearout Mechanisms in Advanced CMOS Technologies, pp.71-208, 2009.
5.
Yung-Hsien Wu, Chia-Lin Ku, Jiun-Fang Wang, "Boron-Retarded Gate Dielectric Formed by Dry Oxidation of Thermal Nitride", Journal of The Electrochemical Society, vol.151, no.1, pp.F1, 2004.
6.
C. Leroux, P. Mur, N. Rochat, D. Rouchon, R. Truche, G. Reimbold, G. Ghibaudo, "Characterization and modeling of nanometric SiO2 dielectrics", Microelectronic Engineering, vol.72, no.1-4, pp.121, 2004.
7.
P. Edelman, A. Savtchouk, M. Wilson, J. D''Amico, J. N. Kochey, D. Marinskiy, J. Lagowski, "Non-contact C-V measurements of ultra thin dielectrics", The European Physical Journal Applied Physics, vol.27, no.1-3, pp.495, 2004.
8.
Samares Kar, "Determination of the Gate Dielectric Capacitance of Ultrathin High-k Layers", Journal of The Electrochemical Society, vol.151, no.7, pp.G476, 2004.
9.
Y. T. Hou, M. F. Li, Y. Jin, W. H. Lai, "Direct tunneling hole currents through ultrathin gate oxides in metal-oxide-semiconductor devices", Journal of Applied Physics, vol.91, no.1, pp.258, 2002.
10.
H. S. Chang, H. D. Yang, H. Hwang, H. M. Cho, H. J. Lee, D. W. Moon, "Measurement of the physical and electrical thickness of ultrathin gate oxides", Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena, vol.20, no.5, pp.1836, 2002.
11.
C Leroux, G Ghibaudo, G Reimbold, R Clerc, S Mathieu, "Oxide thickness extraction methods in the nanometer range for statistical measurements", Solid-State Electronics, vol.46, no.11, pp.1849, 2002.
12.
R. J. Carter, W. Tsai, E. Young, M. Caymax, J. W. Maes, P. J. Chen, A. Delabie, C. Zhao, S. DeGendt, M. Heyns, "Effect of Al-content and Post Deposition Annealing on the Electrical Properties of Ultra-thin HfAlxOy Layers", MRS Proceedings, vol.745, pp.N2.3, 2002.
13.
W.F.A. Besling, E. Young, T. Conard, C. Zhao, R. Carter, W. Vandervorst, M. Caymax, S. De Gendt, M. Heyns, J. Maes, M. Tuominen, Suvi Haukka, "Characterisation of ALCVD Al2O3–ZrO2 nanolaminates, link between electrical and structural properties", Journal of Non-Crystalline Solids, vol.303, no.1, pp.123, 2002.
14.
C. Leroux, G. Ghibaudo, G. Reimbold, R. Clerc, S. Mathieu, "Extraction of oxide thickness in the nanometer range using C(V) characteristics", Microelectronic Engineering, vol.59, no.1-4, pp.277, 2001.
