A physically based compact gate C-V model for ultrathin (EOT /spl sim/1 nm and below) gate dielectric MOS devices

A computationally efficient and accurate physically based gate capacitance model of MOS devices with advanced ultrathin equivalent oxide thickness (EOT) oxides (down to 0.5 nm explicitly considered here) is introduced for the current and near future integrated circuit technology nodes. In such a thin gate dielectric regime, the modeling of quantum-mechanical (QM) effects simply with the assumption of an infinite triangular quantum well at the Si-dielectric interface can result in unacceptable underestimates of calculated gate capacitance. With the aid of self-consistent numerical Schro/spl uml/dinger-Poisson calculations, the QM effects have been reconsidered in this model. The 2/3 power law for the lowest quantized energy level versus field relations (E/sub 1//spl prop/F/sub ox//sup 2/3/), often used in compact models, was refined to 0.61 for electrons and 0.64 for holes, respectively, in the substrate in the regimes of moderate to strong inversion and accumulation to address primarily barrier penetration. The filling of excited states consistent with Fermi statistics has been addressed. The quantum-corrected gate capacitance-voltage (C-V) calculations have then been tied directly to the Fermi level shift as per the definition of voltage (rather than, for example, obtained indirectly through calculation of quantum corrections to the charge centroids offset from the interface). The model was implemented and tested by comparisons to both numerical calculations down to 0.5 nm, and to experimental data from n-MOS or p-MOS metal-gate devices with SiO/sub 2/, Si/sub 3/N/sub 4/ and high-/spl kappa/ (e.g., HfO/sub 2/) gate dielectrics on (100) Si with EOTs down to /spl sim/1.3 nm. The compact model has also been adapted to address interface states, and poly depletion and poly accumulation effects on gate capacitance.

I. Introduction

As THE aggressive scaling of CMOS technology continues, the equivalent physical oxide thickness (EOT) of gate dielectrics is projected by the International Technology Roadmap for Semiconductors (ITRS 2003 Edition) to become as thin as 0.5 nm in some cases in the next 15 years [1]. To overcome the well-known increasingly serious technology difficulties of large gate leakage current and polysilicon related shortcomings (polydepletion, B penetration, etc.), alternative high dielectric constant (high-) materials and metal-gate technology are being considered as replacements for SiO₂ and polysilicon gates, respectively [1]. However, conventional electrical analysis techniques for oxide and MOS devices such as gate capacitance–voltage and gate current–voltage measurements remain important in characterization of gate dielectrics and MOS devices to provide critical information such as dielectric EOT, oxide charge, metal-gate work function, surface doping density, and interface states.