Comparative physical and electrical metrology of ultrathin oxides in the 6 to 1.5 nm regime

In this work, five methods for measuring the thickness of ultra-thin gate oxide layers in MOS structures were compared experimentally on n/sup +/ poly-SiO/sub 2/-p-Si structures. Three methods are based on electrical capacitance-voltage (C-V) and current-voltage (I-V) data and the other two methods are HRTEM and optical measurement. MOS capacitors with oxide thickness in the range 17-55 /spl Aring/ have been used in this study. We found that thickness extracted using QM C-V and HRTEM agree within 1.0 /spl Aring/ over the whole thickness range when a dielectric constant of 3.9 was used. Comparison between thickness extracted using quantum interference (QI) I-V technique and optical measurement were also within 1.0 /spl Aring/ for thickness 31-47 /spl Aring/. However, optical oxide thickness was consistently lower than the TEM thickness by about 2 /spl Aring/ over the thickness range under consideration. Both optical measurement and QM C-V modeling yield the same thickness as the nominal oxide thickness increases (>50 /spl Aring/).