I. Introduction
Moore’s law-driven CMOS device scaling has downscaled field-effect transistors (FETs) to sub-10-nm regime [1], [2]. Post Moore’s law era, the CMOS device designs should be subjected to Koomey’s law for energy efficient chip scaling [3]. The ultradownscaled nonplanar MOS devices are experiencing performance limitations due to short/narrow body effects, increased device random fluctuations, mobility degradation, increased leakage current, and increased interface effects due to high surface-to-volume ratio. To avoid these problems, the semiconductor industry introduced high-k gate dielectrics, silicon-on-insulator (SOI) technology such as fully depleted SOI transistors, and alternative MOS structures such as FinFETs, Si-based gate-all-around nanowire FETs (NWFETs) with both the horizontal and vertical stacks of nanowires for high-performance logic transistors using more Moore scaling [2]. However, current generation nonplanar CMOS devices are suffering from electrothermal (ET) issues such as self-heating effect (SHE) in sub-14-nm node due to low thermal conductivity of gate oxide materials (SiO2 and other high-k materials) and geometrical confinement of the device structure [4]. SHE degrades the transistor performance in terms of lowering the electrostatic integrity, ratio and intrinsic delay. So there is a technological demand to analyze and reduce SHEs in nanoscale MOS devices. In the past decade, many research groups worked on SHE in MOSFETs [5]–[8], FinFETs [9]–[11], NWFETs [12], and multi-Fin FinFETs [13]. However, all these nanoscale MOSFETs have higher surface-to-volume ratio and strongly depends on thermal contact resistance () and interface distribute thermal resistance (), and the above-mentioned effects have not seen with proper investigation in the literature till date.