Ambient Temperature-Induced Device Self-Heating Effects on Multi-Fin Si n-FinFET Performance | IEEE Journals & Magazine | IEEE Xplore

Ambient Temperature-Induced Device Self-Heating Effects on Multi-Fin Si n-FinFET Performance


Abstract:

Device self-heating effects (SHEs) in nonplanar Si MOS transistors such as fin field-effect transistors (FinFETs) and nanowire FETs have become a serious issue in designi...Show More

Abstract:

Device self-heating effects (SHEs) in nonplanar Si MOS transistors such as fin field-effect transistors (FinFETs) and nanowire FETs have become a serious issue in designing well-tempered CMOS devices for future logic nodes. The device thermal contact resistances are strongly influenced by both the ambient temperature and within device lattice temperature. The ambient heat energy coupling through the thermal contact resistances will strongly impact device SHE in FinFETs due to increase in the surface-to-volume ratio of confined geometry thin Si Fin. In this paper, we report a 3-D quantum-corrected electrothermal numerical device analysis involving a coupled hydrodynamic and thermodynamic transport models for a target Si 3-Fin bulk n-FinFET. The numerical device simulations quantitatively predicted the impact of ambient and electrical contact temperatures on device short-channel effect immunity and performance. The simulation parameters are calibrated with the state-of-the-art Si FinFET measurement data from the literature. Our numerical simulation findings establish the phenomena of ambient temperature-induced device SHE on Si n-FinFETs performance for sub-14-nm technology nodes. The simulation predictions establish the fact that the thermal contact resistances and the within-chip ambient temperature (TA) have adverse effects on device lumped thermal resistance (Rth,eff) and performance metrics. Finally, we have numerically analyzed the FinFET design solutions (tapered source and drain regions) to improve the tolerance against the ambient temperature-induced SHE.
Published in: IEEE Transactions on Electron Devices ( Volume: 65, Issue: 7, July 2018)
Page(s): 2721 - 2728
Date of Publication: 21 May 2018

ISSN Information:


I. Introduction

Moore’s law-driven CMOS device scaling has downscaled field-effect transistors (FETs) to sub-10-nm regime [1], [2]. Post Moore’s law era, the CMOS device designs should be subjected to Koomey’s law for energy efficient chip scaling [3]. The ultradownscaled nonplanar MOS devices are experiencing performance limitations due to short/narrow body effects, increased device random fluctuations, mobility degradation, increased leakage current, and increased interface effects due to high surface-to-volume ratio. To avoid these problems, the semiconductor industry introduced high-k gate dielectrics, silicon-on-insulator (SOI) technology such as fully depleted SOI transistors, and alternative MOS structures such as FinFETs, Si-based gate-all-around nanowire FETs (NWFETs) with both the horizontal and vertical stacks of nanowires for high-performance logic transistors using more Moore scaling [2]. However, current generation nonplanar CMOS devices are suffering from electrothermal (ET) issues such as self-heating effect (SHE) in sub-14-nm node due to low thermal conductivity of gate oxide materials (SiO2 and other high-k materials) and geometrical confinement of the device structure [4]. SHE degrades the transistor performance in terms of lowering the electrostatic integrity, ratio and intrinsic delay. So there is a technological demand to analyze and reduce SHEs in nanoscale MOS devices. In the past decade, many research groups worked on SHE in MOSFETs [5]–[8], FinFETs [9]–[11], NWFETs [12], and multi-Fin FinFETs [13]. However, all these nanoscale MOSFETs have higher surface-to-volume ratio and strongly depends on thermal contact resistance () and interface distribute thermal resistance (), and the above-mentioned effects have not seen with proper investigation in the literature till date.

References

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