I. Introduction
In recent years, CMOS process scaling has led to the lowering of supply voltages and has inspired the development of time based quantization techniques as an alternative to voltage based quantization. Among several methods, VCO based quantizers (VCOQ) have become a popular choice for replacing conventional voltage based multibit quantizers. When used as a voltage-to-frequency converter, VCOQs have the desirable properties of inherent first order noise shaping and implicit dynamic element matching (DEM) [1]. Despite the above advantages, the highly nonlinear voltage-to-frequency (V-to-F) transfer characteristic of a VCOQ leads to performance degradation. When the VCOQ is used in a modulator, this nonlinearity degrades the distortion performance and limits the achievable SNDR [1]. In order to suppress the distortion, the order of the loop filter has to be increased more than that required for meeting the quantization noise specification, leading to a higher power consumption and stability issues. To overcome this non-linearity issue, the VCOQ has also been used as a voltage-to-phase converter [2], [3]. Although voltage-to-phase conversion solves the VCOQ non-linearity problem, it requires an explicit DEM which is one of the major power dissipating blocks at GHz range sampling frequencies. Also, introducing a DEM in the feedback path increases the excess-loop-delay (ELD) and sets a limit to the maximum achievable sampling frequency. Digital background calibration [5] has also been used to linearize the VCOQ. The architecture in [4] uses two stages to cancel the VCOQ nonlinearity and implements a second order NTF.