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Terri S. Fiez - IEEE Xplore Author Profile
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Terri S. Fiez

Also published under: T. S. Fiez, T. Fiez, Terri Fiez

Publications
168
Citations
3,612
Publications by Year
19892020
Co-Authors:
Show All Co-Authors (148)
Image of author Terri S. Fiez

Terri S. Fiez

Also published under: T. S. Fiez, T. Fiez, Terri Fiez

Affiliation

Research and Innovation Office Administration
University of Colorado at Boulder
Boulder, USA

Publication Topics

Biography

Terri S. Fiez (M'85–SM'95–F'05) received the B.S. and M.S. degrees in electrical engineering from the University of Idaho, Moscow, ID, USA, in 1984 and 1985, respectively, and the Ph.D. degree in electrical and computer engineering from Oregon State University, Corvallis, OR, USA, in 1990.,She is a Professor of electrical engineering and computer science (EECS) at Oregon State University (OSU). Prior to February 2014, she was Head of the School of EECS for 14 years. She has been involved in starting up and working with startup companies during the last decade. She has been very active professionally as a researcher in high performance analog signal processing integrated circuits and innovative engineering education approaches. She has serve...
Publications
168
Citations
3,612
Publications by Year
19892020
Co-Authors:
Show All Co-Authors (148)
Author's Published Works

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A Highly Linear OTA-Less 1-1 MASH VCO-Based \Delta\Sigma ADC With an Efficient Phase Quantization Noise Extraction Technique

Hamidreza Maghami;Pedram Payandehnia;Hossein Mirzaie;Ramin Zanbaghi;Hossein Zareie;Justin Goins;Siladitya Dey;Kartikeya Mayaram;Terri S. Fiez

IEEE Journal of Solid-State Circuits
Year: 2020 | Volume: 55, Issue: 3 | Journal Article |
Cited by: Papers (24)
In this article, an efficient technique is introduced to extract the quantization noise of a multi-phase voltage-controlled oscillator (VCO)-based quantizer (VCOQ) in the time domain as a pulsewidth modulated (PWM) signal. Using this technique, a new highly linear VCO-based 1-1 multi-stage noise shaping (MASH) delta-sigma analog-to-digital converter (ADC) structure is presented. This architecture ...Show More

A Highly Linear OTA-Less 1-1 MASH VCO-Based $\Delta\Sigma$ ADC With an Efficient Phase Quantization Noise Extraction Technique

Hamidreza Maghami;Pedram Payandehnia;Hossein Mirzaie;Ramin Zanbaghi;Hossein Zareie;Justin Goins;Siladitya Dey;Kartikeya Mayaram;Terri S. Fiez

Year: 2020 | Volume: 55, Issue: 3 | Journal Article |

0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique

Hamidreza Maghami;Pedram Payandehnia;Hossein Mirzaie;Ramin Zanbaghi;Siladitya Dey;Justin Goins;Kartikeya Mayaram;Terri S. Fiez

2019 IEEE Custom Integrated Circuits Conference (CICC)
Year: 2019 | Conference Paper |
Cited by: Papers (2) | Patents (2)
In this paper a novel technique is introduced to extract the quantization noise of a multi-phase VCO-based quantizer (VCOQ) in the time domain as a PWM signal. Using this technique, a new highly linear VCO-based 1-1 MASH delta-sigma ADC structure is presented. This architecture does not require any OTA-based analog integrators or power hungry linearization methods. The first stage is a closed loop...Show More

0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique

Hamidreza Maghami;Pedram Payandehnia;Hossein Mirzaie;Ramin Zanbaghi;Siladitya Dey;Justin Goins;Kartikeya Mayaram;Terri S. Fiez

Year: 2019 | Conference Paper |

A 12 MHz BW, 80 dB SNDR, 83 dB DR, 4th order CT-ΔΣ modulator with 2nd order noise-shaping and pipelined SAR-VCO based quantizer

Siladitya Dey;Kartikeya Mayaram;Terri Fiez

2019 IEEE Custom Integrated Circuits Conference (CICC)
Year: 2019 | Conference Paper |
Cited by: Papers (4)
A 2nd order noise shaping, SAR-VCO based hybrid quantizer is introduced. The SAR quantization error is available as a residue voltage at the end of the SAR conversion. This residue voltage is input to the VCO quantizer. Thus, the non-linear VCO quantizer does not generate harmonic distortion and the hybrid quantizer exhibits high linearity. The SAR and VCOQ operate in a pipeline to reduce excess-l...Show More

A 12 MHz BW, 80 dB SNDR, 83 dB DR, 4th order CT-ΔΣ modulator with 2nd order noise-shaping and pipelined SAR-VCO based quantizer

Siladitya Dey;Kartikeya Mayaram;Terri Fiez

Year: 2019 | Conference Paper |

A Highly Linear OTA-Free VCO-Based 1-1 MASH $\Delta\Sigma$ ADC

Hamidreza Maghami;Pedram Payandehnia;Hossein Mirzaie;Ramin Zanbaghi;Siladitya Dey;Kartikeya Mayaram;Terri S. Fiez

IEEE Transactions on Circuits and Systems I: Regular Papers
Year: 2019 | Volume: 66, Issue: 7 | Journal Article |
Cited by: Papers (10)
In this paper, a new voltage-controlled oscillator (VCO)-based 1-1 MASH delta-sigma ADC structure is presented. The proposed architecture does not require any operational transconductance amplifier-based analog integrators or integrating capacitors. Second-order noise shaping is achieved by using a VCO as an integrator in the feedback loop of the first stage and an open-loop VCO quantizer in the s...Show More

A Highly Linear OTA-Free VCO-Based 1-1 MASH $\Delta\Sigma$ ADC

Hamidreza Maghami;Pedram Payandehnia;Hossein Mirzaie;Ramin Zanbaghi;Siladitya Dey;Kartikeya Mayaram;Terri S. Fiez

Year: 2019 | Volume: 66, Issue: 7 | Journal Article |

A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA

Hossein Mirzaie;Hamidreza Maghami;Ramin Zanbaghi;Pedram Payandehnia;Kartikeya Mayaram;Terri S. Fiez

IEEE Transactions on Circuits and Systems II: Express Briefs
Year: 2019 | Volume: 66, Issue: 3 | Journal Article |
Cited by: Papers (6)
This brief presents the design and implementation of a new blocker tolerant wideband continuous-time delta-sigma modulator. Using a customized digital integrator with inherent data-weighted averaging at the back-end of the modulator, the power consumption of the quantizer is reduced while the speed of operation is increased. Additionally, by using a single amplifier biquad structure in the loop fi...Show More

A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA

Hossein Mirzaie;Hamidreza Maghami;Ramin Zanbaghi;Pedram Payandehnia;Kartikeya Mayaram;Terri S. Fiez

Year: 2019 | Volume: 66, Issue: 3 | Journal Article |

A Novel Time-Domain Phase Quantization Noise Extraction for a VCO-based Quantizer

Hamidreza Maghami;Hossein Mirzaie;Pedram Payandehnia;Kartikeya Mayaram;Ramin Zanbaghi;Terri Fiez

2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)
Year: 2018 | Conference Paper |
Cited by: Papers (3)
A highly linear SAR-VCO MASH delta-sigma ADC architecture is presented. OTA based analog integrators are not needed whereby the ADC is mostly digital and process scaling friendly. A new technique is introduced to extract the quantization noise of the VCO-based quantizer as a PWM signal using digital circuitry. This technique is independent of the OSR and the input signal amplitude of the VCO-based...Show More

A Novel Time-Domain Phase Quantization Noise Extraction for a VCO-based Quantizer

Hamidreza Maghami;Hossein Mirzaie;Pedram Payandehnia;Kartikeya Mayaram;Ramin Zanbaghi;Terri Fiez

Year: 2018 | Conference Paper |

A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta–Sigma Modulator With VCO Quantizer Nonlinearity Cancellation

Siladitya Dey;Karthikeyan Reddy;Kartikeya Mayaram;Terri S. Fiez

IEEE Journal of Solid-State Circuits
Year: 2018 | Volume: 53, Issue: 3 | Journal Article |
Cited by: Papers (26)
A two-stage continuous-time $\Delta \Sigma $ modulator with voltage-controlled oscillator based quantizer (VCOQ) is presented. The presented modulator suppresses the VCOQ voltage-to-frequency nonlinearity through dual path cancellation to achieve high linearity. As an added advantage, this architecture exhibits strong immunity to the first stage quantization error leakage to the output due to ga...Show More

A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta–Sigma Modulator With VCO Quantizer Nonlinearity Cancellation

Siladitya Dey;Karthikeyan Reddy;Kartikeya Mayaram;Terri S. Fiez

Year: 2018 | Volume: 53, Issue: 3 | Journal Article |

Innovation, Startups, and Funding in the Age of Accelerations: A Survey of the Evolving Landscape

Terri S. Fiez;Mar Hershenson;Lucy Sanders;Catherine Ashcraft

IEEE Solid-State Circuits Magazine
Year: 2017 | Volume: 9, Issue: 4 | Magazine Article |
Thomas Friedman's recent book, Thank You for Being Late: An Optimist's Guide to Thriving in the Age of Accelerations, traces how the technology revolution, fueled by the acceleration predicted in Moore's law, has transformed our lives [1]. Friedman celebrates the remarkable advances that have occurred over the past several decades and describes, in layman's terms, the ways in which the solid-state...Show More

Innovation, Startups, and Funding in the Age of Accelerations: A Survey of the Evolving Landscape

Terri S. Fiez;Mar Hershenson;Lucy Sanders;Catherine Ashcraft

Year: 2017 | Volume: 9, Issue: 4 | Magazine Article |

A highly linear OTA-free VCO-based 1-1 MASH ΔΣ ADC

Hamidreza Maghami;Pedram Payandehnia;Hossein Mirzaie;Kartikeya Mayaram;Ramin Zanbaghi;Terri Fiez

2017 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2017 | Conference Paper |
Cited by: Papers (4)
In this paper a new VCO-based MASH delta-sigma ADC structure is presented. The proposed architecture does not require any OTA-based analog integrators or integrating capacitors. Second-order noise shaping is achieved by using a VCO as an integrator in the feedback loop of the first stage and an open loop VCO quantizer in the second stage. Simple digital circuitry extracts the phase quantization er...Show More

A highly linear OTA-free VCO-based 1-1 MASH ΔΣ ADC

Hamidreza Maghami;Pedram Payandehnia;Hossein Mirzaie;Kartikeya Mayaram;Ramin Zanbaghi;Terri Fiez

Year: 2017 | Conference Paper |

A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation

Siladitya Dey;Karthikeyan Reddy;Kartikeya Mayaram;Terri Fiez

2017 IEEE Custom Integrated Circuits Conference (CICC)
Year: 2017 | Conference Paper |
Cited by: Papers (3) | Patents (1)
A two-stage continuous-time (CT) ΔΣ modulator with VCO quantizer (VCOQ) is presented. The presented modulator suppresses the VCOQ Voltage-to-Frequency nonlinearity through dual path cancellation to achieve high linearity. As an added advantage, this architecture exhibits strong immunity to the first stage quantization error leakage to the output due to gain mismatches between the two stages and te...Show More

A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation

Siladitya Dey;Karthikeyan Reddy;Kartikeya Mayaram;Terri Fiez

Year: 2017 | Conference Paper |

JetNet: A proposed protocol for reliable packet delivery in low-power IoT applications

Justin B. Goins;Ankur Guha Roy;Kartikeya Mayaram;Terri S. Fiez

2016 IEEE 3rd World Forum on Internet of Things (WF-IoT)
Year: 2016 | Conference Paper |
The Internet of Things is envisioned to consist of many devices that are all interconnected. In order to achieve this goal, efficient networking techniques are needed that can connect low-power devices to the rest of the world. This paper presents a new protocol that enables sensor networks to efficiently communicate with a base station. The proposed JetNet protocol utilizes a combination of time ...Show More

JetNet: A proposed protocol for reliable packet delivery in low-power IoT applications

Justin B. Goins;Ankur Guha Roy;Kartikeya Mayaram;Terri S. Fiez

Year: 2016 | Conference Paper |

The Red Rag Legacy

Terri S. Fiez

IEEE Solid-State Circuits Magazine
Year: 2016 | Volume: 8, Issue: 4 | Magazine Article |
In 1987, I left Hewlett-Packard Co. to return to graduate school. My first foray into what it meant to be a graduate student was when I met Prof. Dave Allstot at Oregon State University to learn about his research. I walked into his office, and the first thing I saw on his desk was a red periodical. He talked about his research on data converters and gave me a short tutorial. Then he opened up wha...Show More

The Red Rag Legacy

Terri S. Fiez

Year: 2016 | Volume: 8, Issue: 4 | Magazine Article |

A self-clocked blocker-filtering technique for SAW-less wireless applications

Saeed Pourbagheri;Kartikeya Mayaram;Terri S. Fiez

2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
Year: 2016 | Conference Paper |
Cited by: Papers (4)
A blocker filtering technique is presented that extracts the clock from the blocker for SAW-less receivers. The extracted clock is utilized to suppress the blocker without requiring any prior information of the exact location of the blocker. This clock runs at the blocker frequency and drives a notch filter that steers the blocker current away from the signal path. Implemented in a 65 nm CMOS proc...Show More

A self-clocked blocker-filtering technique for SAW-less wireless applications

Saeed Pourbagheri;Kartikeya Mayaram;Terri S. Fiez

Year: 2016 | Conference Paper |

350 mV, 5 GHz Class-D Enhanced Swing Differential and Quadrature VCOs in 65 nm CMOS

Ankur Guha Roy;Siladitya Dey;Justin B. Goins;Terri S. Fiez;Kartikeya Mayaram

IEEE Journal of Solid-State Circuits
Year: 2015 | Volume: 50, Issue: 8 | Journal Article |
Cited by: Papers (11)
A new enhanced swing class-D VCO which operates from a supply voltage as low as 300 mV is presented. The architectural advantages are described along with an analysis for the oscillation frequency. Prototype differential and quadrature variants of the proposed VCO have been implemented in a 65 nm RF CMOS process with a 5 GHz VCO oscillation frequency. At a 350 mV supply, the measured phase noise p...Show More

350 mV, 5 GHz Class-D Enhanced Swing Differential and Quadrature VCOs in 65 nm CMOS

Ankur Guha Roy;Siladitya Dey;Justin B. Goins;Terri S. Fiez;Kartikeya Mayaram

Year: 2015 | Volume: 50, Issue: 8 | Journal Article |

A 3 ppm 1.5 × 0.8 mm 2 1.0 µA 32.768 kHz MEMS-Based Oscillator

Samira Zaliasl;Jim C. Salvia;Ginel C. Hill;Lijun Chen;Kimo Joo;Rajkumar Palwai;Niveditha Arumugam;Meghan Phadke;Shouvik Mukherjee;Hae-Chang Lee;Charles Grosjean;Paul M. Hagelin;Sudhakar Pamarti;Terri S. Fiez;Kofi A. A. Makinwa;Aaron Partridge;Vinod Menon

IEEE Journal of Solid-State Circuits
Year: 2015 | Volume: 50, Issue: 1 | Journal Article |
Cited by: Papers (87)
This paper describes the first 32 kHz low-power MEMS-based oscillator in production. The primary goal is to provide a small form-factor oscillator (1.5 × 0.8 mm 2 ) for use as a crystal replacement in space-constrained mobile devices. The oscillator generates an output frequency of 32.768 kHz and its binary divisors down to 1 Hz. The frequency stability over the industrial temperature range (-40 °...Show More

A 3 ppm 1.5 × 0.8 mm 2 1.0 µA 32.768 kHz MEMS-Based Oscillator

Samira Zaliasl;Jim C. Salvia;Ginel C. Hill;Lijun Chen;Kimo Joo;Rajkumar Palwai;Niveditha Arumugam;Meghan Phadke;Shouvik Mukherjee;Hae-Chang Lee;Charles Grosjean;Paul M. Hagelin;Sudhakar Pamarti;Terri S. Fiez;Kofi A. A. Makinwa;Aaron Partridge;Vinod Menon

Year: 2015 | Volume: 50, Issue: 1 | Journal Article |

A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoM

Ankur Guha Roy;Siladitya Dey;Justin Goins;Kartikeya Mayaram;Terri S. Fiez

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference
Year: 2014 | Conference Paper |
Cited by: Papers (2)
A new enhanced swing class-D quadrature VCO which operates from a supply voltage as low as 350 mV is presented. The prototype 5 GHz VCO was fabricated in a 65 nm RF CMOS process. The measured phase noise performance is -137.1 dBc/Hz at 3 MHz offset with a power dissipation of 2.1 mW from a 0.35 V supply. The resulting figure-of-merit (FoM) is 198.3 dBc/Hz. Compared to prior CMOS LC VCO designs, th...Show More

A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoM

Ankur Guha Roy;Siladitya Dey;Justin Goins;Kartikeya Mayaram;Terri S. Fiez

Year: 2014 | Conference Paper |

A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with −76dBm sensitivity for high data rate wireless sensor networks

Ronghua Ni;Kartikeya Mayaram;Terri S. Fiez

2014 Symposium on VLSI Circuits Digest of Technical Papers
Year: 2014 | Conference Paper |
Cited by: Papers (2) | Patents (1)
A mixer-less low energy BFSK receiver for wireless sensor networks is presented. Q-enhanced frequency-to-amplitude conversion and linear amplification at RF frequencies provide a large conversion gain and high data rates, leading to improved sensitivity and energy efficiency. Fabricated in a 0.13 µm CMOS process, the 915 MHz receiver, with integrated digital calibration, demonstrates a sensitivity...Show More

A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with −76dBm sensitivity for high data rate wireless sensor networks

Ronghua Ni;Kartikeya Mayaram;Terri S. Fiez

Year: 2014 | Conference Paper |

Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test

Masahiro Ishida;Takahiro J. Yamaguchi;Mani Soma;Terri Fiez;Mike Peng Li

2014 IEEE 32nd VLSI Test Symposium (VTS)
Year: 2014 | Conference Paper |
Cited by: Papers (1)
Recent analog designers do think about measurement at design time. Analog design-for-measurement is a real success, not based on test research but based on designers' incorporation of calibration methods to ensure that their circuits work within specifications. In the meantime, mixed-signal test research has not kept pace with new design architectures, and some analog designers have outpaced mixed...Show More

Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test

Masahiro Ishida;Takahiro J. Yamaguchi;Mani Soma;Terri Fiez;Mike Peng Li

Year: 2014 | Conference Paper |

12.9 A 1.55×0.85mm2 3ppm 1.0μA 32.768kHz MEMS-based oscillator

Samira Zali Asl;Shouvik Mukherjee;Will Chen;Kimo Joo;Rajkumar Palwai;Niveditha Arumugam;Preston Galle;Meghan Phadke;Charles Grosjean;Jim Salvia;Haechang Lee;Sudhakar Pamarti;Terri Fiez;Kofi Makinwa;Aaron Partridge;Vinod Menon

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
Year: 2014 | Conference Paper |
Cited by: Papers (6)
Mobile time-keeping applications require small form-factor, tight frequency stability, and micro-power 32.768kHz clock references. Today's 32kHz quartz resonators and oscillators are facing challenges in size reduction. Previously described MEMS-based oscillators can achieve tight accuracy but operate at high frequency with power unsuitable for mobile applications. This paper introduces a 32kHz ME...Show More

12.9 A 1.55×0.85mm2 3ppm 1.0μA 32.768kHz MEMS-based oscillator

Samira Zali Asl;Shouvik Mukherjee;Will Chen;Kimo Joo;Rajkumar Palwai;Niveditha Arumugam;Preston Galle;Meghan Phadke;Charles Grosjean;Jim Salvia;Haechang Lee;Sudhakar Pamarti;Terri Fiez;Kofi Makinwa;Aaron Partridge;Vinod Menon

Year: 2014 | Conference Paper |

A noise-reducing 0.48 nJ/bit interference-robust non-coherent energy detection IR-UWB receiver for wireless sensor networks

Saeed Pourbagheri;Karti Mayaram;Terri Fiez

2013 IEEE MTT-S International Microwave Symposium Digest (MTT)
Year: 2013 | Conference Paper |
A non-coherent interference-tolerant energy detection (ED) IR-UWB receiver with a front-end noise reduction technique is presented. By relaxing the LNA noise requirement, a reduction in power consumption is achieved without sacrificing performance. The fabricated prototype in a 130 nm CMOS process operating with a supply voltage of 1.2 V, achieves the best energy efficiency of 0.48 nJ/bit for ED r...Show More

A noise-reducing 0.48 nJ/bit interference-robust non-coherent energy detection IR-UWB receiver for wireless sensor networks

Saeed Pourbagheri;Karti Mayaram;Terri Fiez

Year: 2013 | Conference Paper |

A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks

Ronghua Ni;Kartikeya Mayaram;Terri S. Fiez

IEEE Journal of Solid-State Circuits
Year: 2013 | Volume: 48, Issue: 5 | Journal Article |
Cited by: Papers (8)
A low power 2.4 GHz hybrid polyphase filter (PPF) based BFSK receiver with high frequency offset tolerance (FOT) at small modulation indexes (MIs) is presented for medium data rate wireless sensor network applications. A high FOT at low MI is achieved by a frequency-to-energy conversion architecture using PPFs without any frequency correction circuits. Channel selection and interference rejection ...Show More

A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks

Ronghua Ni;Kartikeya Mayaram;Terri S. Fiez

Year: 2013 | Volume: 48, Issue: 5 | Journal Article |

An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT $\Delta \Sigma$ Modulator Dissipating 13.7-mW

Ramin Zanbaghi;Pavan Kumar Hanumolu;Terri S. Fiez

IEEE Journal of Solid-State Circuits
Year: 2013 | Volume: 48, Issue: 2 | Journal Article |
A novel low power compact loop filter using a single amplifier biquad (SAB) network is presented for continuous-time (CT) delta-sigma (ΔΣ) modulators. This new technique reduces power consumption and die area by minimizing the number of active elements and simplifying the modulator topology. The new SAB network has a transfer function (TF) zero, which implements a local feedforward (FF) path in sy...Show More

An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT $\Delta \Sigma$ Modulator Dissipating 13.7-mW

Ramin Zanbaghi;Pavan Kumar Hanumolu;Terri S. Fiez

Year: 2013 | Volume: 48, Issue: 2 | Journal Article |

A 2.4GHz hybrid PPF based BFSK receiver with ±180ppm frequency offset tolerance for wireless sensor networks

Ronghua Ni;Kartikeya Mayaram;Terri S. Fiez

2012 Symposium on VLSI Circuits (VLSIC)
Year: 2012 | Conference Paper |
Cited by: Papers (1)
A low-power 2.4GHz 1Mb/s hybrid polyphase filter (PPF) based BFSK receiver with ±180ppm frequency offset tolerance (FOT) and 40dB adjacent channel rejection (ACR) at a modulation index (MI) of 2 is presented. High FOT at low MI is achieved by a frequency-to-energy conversion architecture using PPFs without any frequency correction. The proposed hybrid topology of the PPF provides an improved ACR a...Show More

A 2.4GHz hybrid PPF based BFSK receiver with ±180ppm frequency offset tolerance for wireless sensor networks

Ronghua Ni;Kartikeya Mayaram;Terri S. Fiez

Year: 2012 | Conference Paper |

A 12.5-bit 4 MHz 13.8 mW MASH $\Delta \Sigma$ Modulator With Multirated VCO-Based ADC

Samira Zaliasl;Saurabh Saxena;Pavan Kumar Hanumolu;Kartikeya Mayaram;Terri S. Fiez

IEEE Transactions on Circuits and Systems I: Regular Papers
Year: 2012 | Volume: 59, Issue: 8 | Journal Article |
A novel MASH delta-sigma (ΔΣ) ADC architecture is introduced that has a multirated voltage controlled oscillator (VCO)-based ADC in its second stage. The architecture allows for low power and high speed operation and is insensitive to the VCO linearity. A prototype consists of a first-order switched-capacitor (SC) modulator operating at 100 MHz in the first stage followed by a second-stage VCO-bas...Show More

A 12.5-bit 4 MHz 13.8 mW MASH $\Delta \Sigma$ Modulator With Multirated VCO-Based ADC

Samira Zaliasl;Saurabh Saxena;Pavan Kumar Hanumolu;Kartikeya Mayaram;Terri S. Fiez

Year: 2012 | Volume: 59, Issue: 8 | Journal Article |

A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH $\Delta \Sigma$ Modulator Dissipating 16 mW Power

Ramin Zanbaghi;Saurabh Saxena;Gabor C. Temes;Terri S. Fiez

IEEE Transactions on Circuits and Systems I: Regular Papers
Year: 2012 | Volume: 59, Issue: 8 | Journal Article |
This paper presents a new stage-sharing technique in a discrete-time (DT) 2-2 MASH delta-sigma (ΔΣ) ADC to reduce the modulator power consumption and chip die area. The proposed technique shares all active blocks between the two stages of the modulator. The 2-2 MASH modulator utilizes the second-order Chain of Integrators with Weighted Feed-forward Summation (CIFF) and the Cascade of Integrators w...Show More

A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH $\Delta \Sigma$ Modulator Dissipating 16 mW Power

Ramin Zanbaghi;Saurabh Saxena;Gabor C. Temes;Terri S. Fiez

Year: 2012 | Volume: 59, Issue: 8 | Journal Article |

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