Abstract:
A process for fabricating n-channel JFET/SOS (junction field-effect transistors on silicon-on-sapphire) has been researched. The gate p/sup +/-n junction was obtained by ...Show MoreMetadata
Abstract:
A process for fabricating n-channel JFET/SOS (junction field-effect transistors on silicon-on-sapphire) has been researched. The gate p/sup +/-n junction was obtained by diffusion, and the conductive channel formed by a double ion implantation. Both enhancement and depletion mode transistors were fabricated in different processing conditions. From the results of the Co/sub 60/ /spl gamma/-ray irradiation experiments, we found that the devices had a good total dose radiation hardness. When the total dose was 5 Mrad(Si), their threshold voltages shift was less than 0.1 V. The variation of transconductance and the channel leakage current were also small.
Published in: 1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)
Date of Conference: 23-23 October 1998
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-4306-9
Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China
Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China
Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China
Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China
Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China
Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China
Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China
Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China
Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China
Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China