A process for fabricating n-channel JFET/SOS (junction field-effect transistors on silicon-on-sapphire) has been researched. The gate p/sup +/-n junction was obtained by diffusion, and the conductive channel formed by a double ion implantation. Both enhancement and depletion mode transistors were fabricated in different processing conditions. From the results of the Co/sub 60/ /spl gamma/-ray irra...Show More
CMOS/SOS devices have lower carrier mobility and higher channel leakage current than bulk silicon CMOS devices. These mainly result from the defects in the heteroepitaxial silicon film, especially from the defects near the Si-sapphire interface. This paper describes an experimental study of the improvement in CMOS/SOS devices characteristics resulting from improved epitaxial silicon quality which ...Show More
