Powering Up Dark Silicon: Mitigating the Limitation of Power Delivery via Dynamic Pin Switching

The end of Dennard scaling has led to a large amount of inactive or significantly underclocked transistors on modern chip multiprocessors in order to comply with the power budget and prevent the processors from overheating. This so-called dark silicon is one of the most critical constraints that will hinder the scaling with Moore's Law in future. While advanced cooling techniques, such as liquid cooling, can effectively decrease the chip temperature and alleviate the power constraints, the peak performance, determined by the maximum number of transistors, which are allowed to switch simultaneously, is still confined by the amount of power pins on the chip package. In this paper, we propose a novel mechanism to power up the dark silicon by dynamically switching a portion of I/O pins to power pins when off-chip communications are less frequent. By enabling extra cores or increasing processor frequency, the proposed strategy can significantly boost the performance compared with the traditional designs.

I. Introduction

The continuous shrinking of modern semiconductors has stalled Dennard scaling, which has hitherto sustained the achievement of Moore’s Law over the past few decades. That is, the supply voltage of a transistor – hence the per-transistor switch energy - is no longer scaled with its geometric dimensions [32]. Since the on chip transistor density doubles every 18 months, the chip power is increasing faster than the power delivery system can handle. Consequently, a large portion of transistors need to be significantly under-clocked or even completely turned off to enclose the processor power consumption within a reasonable envelope. This phenomenon, which is termed “utilization wall” or “dark silicon” [20], is predicted to be one of the most critical constraints preventing us from obtaining commensurate performance benefits by adding transistors in the future.