I. Introduction
Fixed point and floating point number representations are being widely used by various applications as in the design of Digital Signal Processors (DSPs). High speed computation with high degree of accuracy are quite essential in a broad range of applications form basic consumer electronics to sophisticated industrial instrumentation. When compared to a fixed point representation, floating point can represent very small and very large numbers, thereby increasing the range of representation. Dynamic range and precision considerations determine whether fixed point or floating point representations are to be used for a specific application. An example, where dynamic range requirements demand the usage of floating point representation is matrix inversion. Various floating point arithmetic operations are extensively supported by all the microprocessors and computer systems. Among various floating point arithmetic operations, multiplication is more frequently used in many applications. The efficient FPGA implementation of complex floating point functions requires the use of efficient multiplication algorithms. An efficient multiplication algorithm, which facilitates optimized utilization of resources and minimum time delay must be used for effective implementation of floating point processors. A floating point multiplier is the most commonly used component in many digital applications such as digital filters, data processors and DSPs. About 37 % of the floating point instructions in benchmark applications constitute floating point multiplications [1].