Contents I. Introduction
As the VLSI technology entered the sub 10nm regime, challenges in mitigating the parasitic effects to have the optimum gate controllability has increased many folds. As discussed in many reported works, the removal of junction from the devices can be a potential solution for optimal control of gate. The MOSFET structure without junctions, also known as Junctionless field effect transistor (JLFET), has been explored widely in the last decade for possible use in VLSI Industry [1–2]. JLFET shows outstanding performance in the ON-state with the extremely low conduction loss as the whole body of the device conducts and the only one significant source of resistance which is the resistance of the body material itself while other structures have additional resistances sourced from the junction [3–4]. However, the OFF-characteristics may have some drawbacks if the thickness of the channel is more. A thin and narrow channel may not have significant offstate loss but to get higher drive current, it is required to have a thicker channel [5]. Some works on enhancing the OFF-characteristics without or minimally affecting the ON-characteristics have been reported so far. The use of high k -dielectric and -spacer are some techniques for enhancing OFF-characteristics [6–7]. Placing a dielectric layer at the centre of the channel is another technique which can reduce OFFstate current significantly [8]. Most of these techniques may not be possible to implement beyond a limit. For example, there are only few dielectrics which can be interfaced with a semiconductor material. By making the semiconductor region under the gate thinner compared to source drain region may significantly reduce the OFF-state leakage current. As the source drain regions are thicker, the ON resistance will also remain lower and the conduction loss will not increase significantly. Therefore, this paper studies a JLFET with a thinner channel and thicker source-drain region.
