A Dual-Material Gate Junctionless Transistor With High- $k$ Spacer for Enhanced Analog Performance

In this paper, we present a simulation study of analog circuit performance parameters for a symmetric double-gate junctionless transistor (DGJLT) using dual-material gate along with high- k spacer dielectric (DMG-SP) on both sides of the gate oxides of the device. The characteristics are demonstrated and compared with DMG DGJLT and single-material (conventional) gate (SMG) DGJLT. The DMG DGJLT presents superior transconductance (Gm), early voltage (VEA), and intrinsic gain (GmRO) compared with SMG DGJLT. The values are further improved for DMG-SP DGJLT, because high- k spacer enhances the fringing electric fields through the spacer.

I. Introduction

The Conventional metal–oxide–semiconductor field-effect transistors (MOSFETs) impose challenges, such as enlarged gate leakage and added serious short-channel effects (SCEs) with the continuous miniaturization of device sizes at nanoscale regime. Multiple gate FETs have better scalability due to its superior controllability of the gates on the channel region. However, very abrupt source and drain junctions requirement put challenges in doping profile techniques and thermal budget. Junctionless transistor (JLT), which does not have p-n junction in the source–channel–drain path, has better SCEs performance resulting better scalability, greatly simplified process flow, low thermal budgets after gate formation, and so on [1]–[4]. However, JLTs suffer from lesser drain current and transconductance compared with inversion mode MOSFETs due to high doping concentration in the channel region [1], [5], [6].