Positive Bias Instability and Recovery in InGaAs Channel nMOSFETs

Instability of InGaAs channel nMOSFETs with the Al₂O₃/ ZrO₂ gate stack under positive bias stress demonstrates recoverable and unrecoverable components, which can be tentatively assigned to the pre-existing and generated defects, respectively. The recoverable component is determined to be primarily associated with the defects in the Al₂O₃ interfacial layer (IL), the slow trapping at which is responsible for the power law time dependency of the threshold voltage shift and transconductance change. The fast electron trapping in the ZrO₂ film exhibits negligible recovery, in contrast to the Si-based devices with a similar high-k dielectric film. Generation of new electron trapping defects is found to occur in the IL, preferentially in the region close to the substrate, while trap generation in the high-k dielectric is negligible.

I. Introduction

The III-V channel transistors are a promising option for the logic devices for future 7 nm and beyond technology nodes due to their high electron mobility and low power operations [1], [4]. While there is a growing consensus on the use of InGaAs as a channel material, fabricating high quality gate dielectric stacks on this type of substrates presents one of the major challenges for practical implementation of III-V devices [5]. In this paper, we report the PBTI study on the 53% InGaAs channel NFETs with the gate dielectric and thin interfacial film, focusing on identifying the sources of instability, which might require a special attention from the device fabrication standpoint.