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D. Veksler - IEEE Xplore Author Profile

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Defect generation controlling device degradation is found to be highly sensitive to the signal duration in circuitry-relevant operation frequencies (GHz). Stressing devices in ns-time range reveals greatly extended device lifetimes compared to conventional evaluation conditions. The role of energy generation/dissipation in scaled devices is discussed.Show More
Resistive switching in 2D materials such as hexagonal boron nitride (hBN) and Transition Metal Dichalcogenides (TMDs) have been demonstrated recently [1]–[3]. These memory devices with an ultra-thin switching layer have the potential to achieve low operating voltages, low variability and are also suitable for flexible electronic applications [4]. Here we report the first experimental observation o...Show More
A simulation package for CNT memory cells is developed, based on computational modeling of both the mesoscopic structure of carbon nanotube films and the electrical conductivity of inter-CNT contacts. The developed package enables the modeling of various electrical measurements and identification of a range of operation conditions delivering desirable device characteristics. This approach opens th...Show More
Root-cause of instability in carbon nanotubes memristors is analyzed employing ultra-short pulse technique in combination with atomic-level material modeling. Separating various factors affecting switching operations allowed to identify structural features and operational conditions leading to improved cell characteristics.Show More
Carbon nanotubes (CNT) resistance-change memory devices were assessed for neuromorphic applications under high frequency use conditions by employing the ultra-short (100 ps -10 ns) voltage pulse technique. Under properly selected operation conditions, CNTs demonstrate switching characteristics promising for various NN implementations.Show More
Switching variability in polycrystalline compliance-free HfO2-based 1R RRAM is evaluated employing ultra-fast low voltage pulse approach. Changes in filament conductivity are linked to the variations of energy consumed in a switching process. This study indicates that variability is reduced (suppressed) in more resistive filaments.Show More
We observe a gamma-irradiation-induced change in electrically detected magnetic resonance (EDMR) in TiN/Ti/HfO2/TiN resistive random access memory (RRAM). EDMR measurements exclusively detect electrically active defects, which are directly involved in the transport mechanisms within these devices. The EDMR response has an isotropic g value of 2.001 ± 0.0003. The response increases dramatically wit...Show More
To combat the large variability problem in resistive random access memory, current compliance elements are commonly used to limit the in-rush current during the forming operation. Regardless of the compliance element (1R-1R or 1T-1R), some degree of current overshoot is unavoidable. The peak value of the overshoot current is often used as a predictive metric of the filament characteristics and is ...Show More
Charge-capture/emission is ubiquitous in electron devices. Its dynamics often play critical roles in device operation and reliability. Treatment of this basic process is found in many text books and is considered well understood. As in many electron device models, the individuality of immobile charge is commonly replaced with the average quantity of charge density. This has worked remarkably well ...Show More
High-mobility alternative channel materials to silicon are critical to the continued scaling of MOS devices. The analysis of capacitance–voltage (C–V) measurements on these new materials with high-k gate dielectrics is a critical technique to determine many important gate-stack parameters. While there are very useful C–V analysis tools available to the community, these tools are all limited in the...Show More
The stochastic nature of the conductive filaments in oxide-based resistive memory resistive random access memory (RRAM) represents a sizeable impediment to commercialization. As such, program-verify methodologies are highly alluring. However, it was recently shown that the program-verify methods are unworkable due to strong resistance state relaxation after SET/RESET programming. In this letter, w...Show More
Most experimental reports of tunneling field-effect transistors show defect-related performance degradation. Charging of oxide traps causes Fermi-level pinning, and Shockley-Read-Hall (SRH)/trap-assisted tunneling (TAT) cause unwanted leakage current. In this paper, we study these degradation mechanisms using the pulsed I-V technique. Our simulations show pulsed I-V can fully suppress oxide trap c...Show More
We report on new fluctuation dynamics of the high resistance state of Hafnia-based RRAM devices after RESET. We observe that large amplitude fluctuations occur more frequently immediately after programming and their frequency of occurrence decays in the tens of microseconds. The fluctuation amplitude, on the other hand, does not decay noticeably over the entire millisecond read time. While post-pr...Show More
In this letter, we use gated Hall method for direct measurement of free carrier density and electron mobility in inversion InGaAs MOSFET channels. At room temperature, the highest Hall mobility of 1800 cm2/Vs is observed at electron density in the channel $\approx 1\times 10^{12}$ cm $^{-2}$ . A comparison with mobility values estimated from transistor characteristics reveals a significant under...Show More
A methodology for the evaluation of ultra-fast interfacial traps, using jitter measurements as a probe, is developed. This methodology is applied to study the effect of PBTI stress on the density of ultra-fast electron traps (with 500 ps to 5 ns characteristic capture/emission times) in a high-k/Si nMOSFET. It is shown, that in spite of an observed increase of timing jitter after PBTI stress, this...Show More
Spatial and temporal variability of HfOx-based resistive random access memory (RRAM) are investigated for manufacturing and product designs. Manufacturing variability is characterized at different levels including lots, wafers, and chips. Bit-error-rate (BER) is proposed as a holistic parameter for the write cycle resistance statistics. Using the electrical in-line-test cycle data, a method is dev...Show More
In this work we apply a new spectroscopic technique based on the simulation of capacitance and conductance measurements to investigate the defect density in high-κ/III-V MOSFETs. This technique exploits the simulation of C-V and G-V curves measured over a wide frequency range to extract the defect density map in the energy-position domain. The technique was used to investigate the role of the subs...Show More
We report on the impact of H2 high-pressure annealing (HPA) onto In0.7Ga0.3As MOSCAPs and quantum-well (QW) MOSFETs with Al2O3/HfO2 gate-stack. After HPA with process condition of 300°C, H2 ambient and pressure of 20 atm, we observed notable improvements of the capacitance-voltage (CV) characteristics in InGaAs MOSCAPs with Al2O3/HfO2 gate-stack, such as reduction of equivalent-oxide-thickness and...Show More
We present a comprehensive simulation framework to interpret electrical characteristics (I-V, C-V, G-V, Charge-Pumping, BTI, CVS, RVS, ∶) commonly used for material characterization and reliability analysis of gate dielectric stacks in modern semiconductor devices. By accounting for the physical processes controlling charge transport through the dielectric (e.g. carrier trapping/de-trapping at the...Show More
The distributed oxide trap model based on tunneling of carriers from the semiconductor surface is unified with the two-band Shockley-Read-Hall type of capture and emission model for interface states. The new model explains the often observed upturn of MOS conductance at high frequencies when biased in inversion. The unified two-band model fully covers both types of charge traps in all MOS bias reg...Show More
We propose a new defect characterization technique for high-k dielectric stacks in III-V MOSFETs. This technique allows extracting the defect density from the simulations of the C-V and G-V characteristics at different frequencies. The simulation is performed using a physical distributed compact model, where the trap-assisted capture and emission processes are described in the framework of the mul...Show More
We report on a methodology to assist fabrication process development using a case study of high thermal budget (HTB) and low thermal budget (LTB) fabrication flows for high-k/metal gate stacks in n-MOSFETs. This methodology is supported by simulations that self-consistently extract defect characteristics by simultaneously considering a set of electrical measurement data, specifically stress-induce...Show More
We investigate a possibility that changes of electrical characteristics of the nFETs high-k gate stacks under moderate voltage stresses are induced primarily by a reversible activation of the pre-existing defects rather than generation of new structural defects. These electrically silent pre-cursor defects become responsible for measured stress-induced instabilities of transistor parameters after ...Show More
Increased CMOS performance requires the introduction of alternative materials as substrate and gate dielectrics. III-V materials and in particular InGaAs can provide superior electron mobility compared to classic Si substrates. However, such substrate materials have non-optimal dielectric-semiconductor interfaces that can drastically reduce the device performance. Techniques for the extraction of ...Show More