Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience | IEEE Journals & Magazine | IEEE Xplore

Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience


Abstract:

As dynamic variability increases with CMOS scaling, it is essential to incorporate large design-time timing margins to ensure yield and reliable operation. Online techniq...Show More

Abstract:

As dynamic variability increases with CMOS scaling, it is essential to incorporate large design-time timing margins to ensure yield and reliable operation. Online techniques for timing error resilience help recover timing margins, improving performance and/or power consumption. This paper presents TIMBER, a technique for online timing error resilience that masks timing errors by borrowing time from successive pipeline stages. TIMBER-based error masking can recover timing margins without instruction replay or roll-back support. Three sequential circuit elements are described: TIMBER flip-flop, dedicated TIMBER flip-flop, and TIMBER latch. The TIMBER flip-flop uses two master latches and one slave latch to mask timing errors by borrowing discrete units of time from successive pipeline stages. It can be simplified to a dedicated TIMBER flip-flop that uses only two latches for time-borrowing (TB) at the expense of the flexibility of configuration as a conventional master-slave flip-flop. The TIMBER latch masks timing errors through continuous time-borrowing from successive pipeline stages, and supports runtime configuration as a conventional master-slave flip-flop. The TIMBER latch's continuous time-borrowing capability provides better time-borrowing capabilities at lower hardware cost, but the TIMBER flip-flop's discrete time-borrowing capability preserves the edge triggering property of a flip-flop, thus blocking the propagation of glitches and spurious transitions. In addition to evaluating the overhead and tradeoffs of TIMBER-based error masking on an industrial processor, the three circuits were also prototyped on an FPGA and their timing error masking capability was validated using a two-stage pipeline test structure.
Published in: IEEE Transactions on Computers ( Volume: 63, Issue: 2, February 2014)
Page(s): 497 - 509
Date of Publication: 02 August 2012

ISSN Information:

References is not available for this document.

1 Introduction

As static and dynamic variability effects increase with technology scaling, the timing margins that are added to compensate for worst case static and dynamic variability effects are also increasing [1]. Design-time techniques to address static variability based on clock skew adjustment [2], soft-edge flip-flops [3], and latches [4] have been proposed in the literature. Postmanufacturing techniques like speed-binning can also reduce the timing margins necessary to offset static variability sources like process variations by assigning a different voltage/frequency to each chip during manufacturing test. This is possible because static variability sources do not change with time and are also workload independent. However, dynamic variability is both time and workload dependent. As a result, there is significant interest in solutions that provide runtime resilience to timing errors, thereby recovering the timing margins necessary to offset dynamic variability effects.

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References

References is not available for this document.