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Kartik Mohanram - IEEE Xplore Author Profile

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Computing systems that integrate advanced non-volatile memories (NVMs) are vulnerable to several security attacks that threaten (i) data confidentiality, (ii) data availability, and (iii) data integrity. This paper proposes Architectures for Smart Security of NVMs (AS-SET), which integrates five low overhead, high performance security solutions-SECRET [1], COVERT [2], ACME [3], ARSE-NAL [4], and S...Show More
Modern memory systems are susceptible to data confidentiality attacks that leverage memory access pattern information to obtain secret data. Oblivious RAM (ORAM) is a secure cryptographic construct that effectively thwarts access-pattern-based attacks. However, in Path ORAM (state-of-the-art efficient ORAM for main memories) and its variants, each memory request (read or write) is transformed to a...Show More
RAPID is a low-overhead critical-word-first read acceleration architecture for improved performance and endurance in MLC/TLC non-volatile memories (NVMs). RAPID encodes the critical words in a cache line using only the most significant bits (MSbs) of the MLC/TLC NVM cells. Since the MSbs of an NVM cell can be decoded using a single read strobe, the data (i.e., critical words) encoded using the MSb...Show More
Modern computing systems that integrate emerging non-volatile memories (NVMs) are vulnerable to classical security threats to data confidentiality (e.g., stolen DIMM and bus snooping attacks) as well as new security threats to system availability (e.g., denial of memory service (DoMS) attacks). Although counter mode encryption (CME) secures NVM-based main memories against confidentiality attacks, ...Show More
CASTLE is a Compression-based main memory Architecture realizing a read-decrypt-free (i.e., write-only) Secure solution for low laTency, Low Energy, high endurance non-volatile memories (NVMs). CASTLE integrates pattern-based data compression and incomplete data mapping (i.e., expansion coding) to improve NVM energy, latency, and lifetime without impacting the security guarantees of the underlying...Show More
Whereas emerging non-volatile memories (NVMs) are low power, dense, scalable alternatives to DRAM, the high latency and low endurance of these NVMs limit the feasibility of NVM-only memory systems. Smart hybrid memories (SHMs) that integrate NVM, DRAM, and on-module processor logic are an efficient means to bridge the latency and endurance gaps between NVM-only and DRAM-only memory systems. Howeve...Show More
Whereas data persistence in non-volatile memories (NVMs) enables instant data recovery (IDR) in the face of power/system failures, it also exposes NVMs to data confidentiality and integrity attacks. Counter mode encryption and Merkle Tree authentication are established measures to thwart data confidentiality and integrity attacks, respectively, in NVMs. However, these security mechanisms require h...Show More
With technology scaling, phase change memory (PCM) has become highly vulnerable to write disturbance (WD) errors. A PCM WD error occurs when a cell write dissipates heat to idle cells in the same/adjacent word lines (WLs), disturbing the states of those cells. Whereas state-of-the-art solutions, e.g., data insulation (DIN) and super dense PCM (SD-PCM), have successfully addressed WL PCM WD errors,...Show More
Data confidentiality attacks utilizing memory access patterns threaten exposure of data in modern main memories. Oblivious RAM (ORAM) is an effective cryptographic primitive developed to thwart access-pattern-based attacks in DRAM-based systems. However, in emerging non-volatile memory (NVM) systems, the increased writes due to encryption of multiple data blocks on every Path ORAM (state-of-the-ar...Show More
Data tampering threatens data integrity in emerging non-volatile memories (NVMs). Whereas Merkle Tree (MT) memory authentication is effective in thwarting data tampering attacks, it drastically increases cell writes and memory accesses, adversely impacting NVM energy, lifetime, and system performance (instructions per cycle (IPC)). We propose ASSURE, a low overhead, high performance Authentication...Show More
In this paper, we propose new techniques for the secure storage of transport data consisting of vehicles, registrations and payments in the e-Services Web Portal of Transport Department. For this purpose, new secure and effective storage techniques are proposed in this paper in order to store the data efficiently and to retrieve them fast. The proposed techniques have been tested, using Tamil Nadu...Show More
The increased capacity of multi-/triple-level cells (mlc/tlc) in phase change memory (pcm) comes at the cost of higher write latency and energy, primarily due to consecutive short programming pulses in the pcm program-and-verify (p&v) approaches. l3ep is a regression-based low latency, low energy tlc pcm p&v solution. l3ep reaches the target tlc state in just one (at most five) pulse(s) for up to ...Show More
Security vulnerabilities arising from data persistence in emerging non-volatile memories (NVMs) necessitate memory encryption to ensure data security. Whereas counter mode encryption (CME) is a stop-gap practical approach to address this concern, it suffers from frequent memory re-encryption (system freeze) for small-sized counters and poor system performance for large-sized counters. CME thus imp...Show More
This paper describes a virtual two-port memory architecture for emerging asymmetric non-volatile memory technologies. Realized using only conventional single-port memory cells that provide excellent scalability and density, virtual two-porting delivers the speed and bandwidth of physical two-port memory for just 1.8% of the cost of physical two-porting. Performance analysis of the SPEC CPU2006 ben...Show More
Reliability continues to be a severe challenge in the development of emerging memories. In this article, the authors offer a comprehensive survey of reliability enhancement techniques for three mainstream emerging memories and a summary of the possible future research directions in this area.Show More
Data persistence in emerging non-volatile memories (NVMs) poses a multitude of security vulnerabilities, motivating main memory encryption for data security. However, practical encryption algorithms demonstrate strong diffusion characteristics that increase cell flips, resulting in increased write energy/latency and reduced lifetime of NVMs. State-of-the-art security solutions have focused on redu...Show More
This paper describes a low overhead, offline frequent value encoding (FVE) solution to reduce the write energy in multi-level/triple-level cell (MLC/TLC) non-volatile memories (NVMs). The proposed solution, which does not require any runtime software support, clusters a set of general-purpose applications according to their data frequency profiles and generates a dedicated offline FVE that minimiz...Show More
Multi-level/triple-level cell non-volatile memories (MLC/TLC NVMs) such as PCM and RRAM are the subject of active research and development as replacement candidates for DRAM, which is limited by its high refresh power and poor scaling potential. Besides the benefits of non-volatility (low refresh power) and improved scalability, MLC/TLC NVMs offer high data density and memory capacity over DRAM. H...Show More
Partial data mapping (PDM) is an effective means to reduce the energy/latency of multi-level/triple-level cell non-volatile memories (MLC/TLC NVMs) by excluding high energy/latency MLC/TLC states. This paper proposes energy efficient error recovery (E3R) to simultaneously extend the lifetime and lower the energy/latency of PDM MLC/TLC NVMs. E3R partitions NVM rows into segments that remain in the ...Show More
This paper describes a write-once-memory-code phase change memory (WOM-code PCM) architecture for next-generation non-volatile memory applications. Specifically, we address the long latency of the write operation in PCM-attributed to PCM SET-by proposing a novel PCM memory architecture that integrates the 〈22}2/3 WOM-code at the memory organization and memory controller levels. To further improve ...Show More
The increased capacity of multi-level cells (MLC) in emerging nonvolatile memory (NVM) technologies comes at the cost of higher cell write energies and lower cell endurance. In this paper, we describe MFNW, a Flip-N-Write encoding solution that effectively reduces the average write energy and improves endurance of MLC NVMs. Two MFNW modes are proposed and analyzed: cell Hamming distance (CHD) mode...Show More
Vertical monolayer heterojunction FETs based on transition metal dichalcogenides (TMDCFETs) and planar black phosphorus FETs (BPFETs) have demonstrated excellent sub-threshold swing, high ION/IOFF, and high scalability, making them attractive candidates for post-CMOS memory design. This paper explores TMDCFET and BPFET SRAM design by combining atomistic self-consistent device modeling with SRAM ci...Show More
Asymmetry in read/write access latencies, which leads to issues of blocking writes and low throughput performance, is a common challenge impeding the integration of emerging nonvolatile memory technologies into high-performance computing systems. Approaches based on multiporting and virtually pipelined architectures, which have been studied in static random access memory (SRAM)/dynamic random acce...Show More
This paper proposes a compression-based architecture for bit-write reduction in emerging non-volatile memories (NVMs). Bit-write reduction has many practical benefits, including lower write la-tency, lower dynamic energy, and enhanced endurance. The proposed architecture, which is integrated into the NVM module, relies on (i) a frequent pattern compression-decompression engine, (ii) a comparator t...Show More
This paper describes a write-once-memory-code phase change memory (WOM-code PCM) architecture for next-generation non-volatile memory applications. Specifically, we address the long latency of the write operation in PCM — attributed to PCM SET — by proposing a novel PCM memory architecture that integrates WOM-codes at the memory organization and memory controller levels. The proposed 2/3 WOM-c...Show More