Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels

In this letter, we have investigated experimentally, for the first time, the feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. In situ doped poly-Si material features high and uniform-doping concentration, facilitating the fabrication process. The developed JL device exhibits desirable electrostatic performance in terms of higher ON/OFF current ratio and lower source/drain series resistance as compared with the inversion-mode counterpart. Such scheme appears of great potential for future system-on-panel and 3-D IC applications.

I. Introduction

Polycrystalline silicon (poly-Si) thin-film transistors (TFTs) have become very attractive for future 3-D electronics integration due to the low deposition temperature and mature fabrication processes [1], [2]. Recently, the adoption of nanowires (NWs) as the channel in TFTs has demonstrated superior performance, owing to their small volume and the accompanying reduction in defects [3], [4]. Moreover, when combined with multiple gate (MG) configuration, the NW device manifests enhanced drive current and subthreshold slope (), as well as good immunity to short-channel effects, because the gates can effectively control the electrostatic potential in the ultrathin channel, so that the channel suffers from less electrical interference between the source and drain [5], [6]. The MG field-effect transistor (FET) with NW channel is thus considered as one of the promising next-generation nanostructure devices. However, as the device size is continuously scaled down, the formation of extremely abrupt junctions between the source/drain (S/D) and channel regions is still very challenging, even for the NW FETs when operating in the inversion-mode (IM) regime. To circumvent this problem, we propose an NWFET with gate-all-around (GAA) structure using one in situ doped poly-Si layer to form source, NW channel, and drain regions without additional implantation procedure. Such structure is basically an accumulation-mode transistor and also named junctionless (JL) transistor [7], [8] because, essentially, no junction is contained throughout the device, and therefore, this mitigates the requirement of precise control of dopant concentration profile in the S/D regions. By taking advantage of the tiny body of NW channels and GAA configuration, excellent on–off characteristics are demonstrated in this letter. Fig. 1.

Illustration of the key steps for forming the NW devices. (a) Formation of sub-100-nm cavities underneath the top nitride layer at the two sides of a nitride/oxide/nitride stack before active layer deposition. (b) Schematic of a JL poly-Si NW device. (c) Schematic of an IM poly-Si NW device. (b) and (c) are the temporary structures before the formation of the all-around gate.