Dual-Material Double-Layer Gate Stack SON MOSFET: A Novel Architecture for Enhanced Analog Performance—Part II: Impact of Gate-Dielectric Material Engineering

Part I of this paper dealt with the simulation study, using ATLAS 2D, of analog-circuit performance metrics for the dual-material-gate (DMG) silicon-on-nothing (SON) MOSFET. It was reported that, out of the several combinations in the DMG design studied, the DMG device with L_M1/ L ratio as 1/2 amalgamates the advantages of using a high metal work-function gate M1 and low metal work-function gate M2 in the most efficient manner. This paper focuses upon the effect of double-layer gate stack (DGS) (high-k/SiO₂) on the single-material-gate (SMG) SON and the DMG SON MOSFETs. Improved Early voltage and reduced output conductance of the DMG SON MOSFETs are the driving forces behind the observed increase in intrinsic gain and f_T-gain relationship for the DMG devices over SMG SON MOSFETs, with the DMG SON MOSFETs having L_M1/L ratio as 1/2, proving to be the best choice among various L_M1/L ratios studied. A further improvement in intrinsic gain in DMG DGS SON MOSFETs comes about because of increased gate control on the channel, thus establishing design guidelines aiming at higher gain and better f_T-gain relationship.

I. Introduction

In ORDER to reduce gate leakage current and meet the off-state leakage-current requirements, high- dielectrics as an alternative to replace as the gate dielectric are clearly required to scale beyond the 45-nm node as indicated in the International Roadmap for Semiconductors [1]. A thin passivating layer of between bulk and high- dielectric, so as to form a gate-dielectric stack, is a good approach to balance between the advantages and limitations of high-/Si system [2], [3]. The principal challenge that has impeded implementation of high- is the threshold-voltage offset observed when high- dielectrics are integrated with polysilicon gate electrodes [4], [5]. Metal gate electrodes are expected to greatly mitigate or eliminate the threshold-voltage offset [6], [7] and serve to provide an alternative solution to various problems like polysilicon-depletion-width effect, dopant penetration, and compatibility problems of high- /polysilicon system [8]–[10].