Contents I. Introduction
In ORDER to reduce gate leakage current and meet the off-state leakage-current requirements, high- dielectrics as an alternative to replace as the gate dielectric are clearly required to scale beyond the 45-nm node as indicated in the International Roadmap for Semiconductors [1]. A thin passivating layer of between bulk and high- dielectric, so as to form a gate-dielectric stack, is a good approach to balance between the advantages and limitations of high-/Si system [2], [3]. The principal challenge that has impeded implementation of high- is the threshold-voltage offset observed when high- dielectrics are integrated with polysilicon gate electrodes [4], [5]. Metal gate electrodes are expected to greatly mitigate or eliminate the threshold-voltage offset [6], [7] and serve to provide an alternative solution to various problems like polysilicon-depletion-width effect, dopant penetration, and compatibility problems of high- /polysilicon system [8]–[10].
