Contents I. Introduction
As the nanoelectronic industry moves towards reducing the dimension of the CMOS-based devices to develop much denser circuit, more practical and low-cost chips, the prospect of exploring novel transistor architectures enabling improved commutation speed, analog and RF performances becomes more realistic [ 1 – 6 ]. In this context, further downscaling of transistors has encountered extensive challenges related to several undesired effects including short channel effects (SCEs) and HCEs, which lead to degrade the transistor performance and life-time [ 4 – 7 ]. Alternatively, an emerging strategy for addressing these shortfalls is to incorporate multigate designs to promote strong gate control, thus allowing the possibility to effectively suppress SCEs [ 6 – 9 ]. Despite this advantage of multi-gate devices, the elaboration of abrupt PN junction at the source/drain sides is extremely challenging when shrinking down the gate length to sub-100nm, making the conventional design too upstream to yet contemplate potential incorporating in future nanoelectronic circuit design [ 9 – 11 ]. Accordingly, the emerging field of Junctionless devices, a technology that suggests the use of a uniform channel doping profile to avoid the establishment of P/N junctions, is promising to achieve the desired enhancements concerning the device manufacturing process [ 7 – 9 ]. However, GAAJL MOSFET devices still suffer from several problems including the low derived current capability, degraded analog and RF performances, the high leakage current and the degradation related to HCEs [ 11 – 13 ]. Therefore, research efforts should be focused on two essential objectives: the first one relies on designing new GAAJL MOSFET structures to achieve high drain current and suitable analog/RF performances the other deals with exploring alternative pathways for eliminating the undesired HCEs while reaching reduced power consumption. For this purpose, worldwide researchers are establishing the groundwork for this path, where various strategies like inserting high-k dielectric, Hetero-Dielectric oxide engineering, gate engineering and drain/source extensions are proposed [ 13 – 15 ]. However, these approaches have been applied either to improve the transistor analog/RF performances or to address the reliability against HCEs, although it is believed that these concepts are considered complimentary to predict the degradation behavior of the GAAJL MOSFET for high-performance and reliable analog/RF applications. Besides, the investigation of the device reliability behavior through device elaboration and experimental testing is considered expensive and time consuming, which has inspired turning out towards the use of accurate analytical modeling and/or numerical simulations. In this work, compact models of GAAJL MOSFET incorporating the effect of HCEs are developed to predict the device performance under damage conditions. The obtained results emphasize the ability of the proposed approach to accurately predict the performance of GAAJL MOSFET design including the degradation related to HCEs, thus offering an efficient tool to the designer for selecting the appropriate architecture according to the envisaged application. Therefore, the proposed design methodology can be implemented in device simulators to deeply investigate and optimize the transistor performance for designing reliable nanoelectronic circuits.
