CNTFET Modeling and Reconfigurable Logic-Circuit Design | IEEE Journals & Magazine | IEEE Xplore

CNTFET Modeling and Reconfigurable Logic-Circuit Design


Abstract:

This paper examines aspects of design technology required to explore advanced logic-circuit design using carbon nanotube field-effect transistor (CNTFET) devices. An over...Show More

Abstract:

This paper examines aspects of design technology required to explore advanced logic-circuit design using carbon nanotube field-effect transistor (CNTFET) devices. An overview of current types of CNTFETs is given and highlights the salient characteristics of each. Compact modeling issues are addressed and new models are proposed implementing: 1) a physics-based calculation of energy conduction sub-band minima to allow a realistic analysis of the impact of CNT helicity and radius on the dc characteristics; 2) descriptions of ambipolar behavior in Schottky-barrier CNTFETs and ambivalence in double-gate CNTFETs (DG-CNTFETs). Using the available models, the influence of the parameters on the device characteristics were simulated and analyzed. The exploitation of properties specific to CNTFETs to build functions inaccessible to MOSFETs is also described, particularly with respect to the use of DG-CNTFETs in fine-grain reconfigurable logic.
Published in: IEEE Transactions on Circuits and Systems I: Regular Papers ( Volume: 54, Issue: 11, November 2007)
Page(s): 2365 - 2379
Date of Publication: 12 November 2007

ISSN Information:

References is not available for this document.

I. Introduction

The pursuit of moore's law, as predicted by the International Technology Roadmap for Semiconductors (ITRS) has pointed to significant future intrinsic device hurdles (such as leakage, interconnect, power, quantum effects) to the capability of realizing system architectures using CMOS transistors with the performance levels required by future applications. It is recognized that these limitations, as much fundamental as economic, require the semiconductor industry to explore the use of novel materials and devices able to complement or even replace the CMOS transistor in systems on chip within the next decade and before silicon based technology will reach its limits in 2020 when the channel length of MOSFET is below 10 nm.

Select All
1.
D. Rondoni and J. Hoekstra, "Towards models for CNT devices", Proc. IEEE RISC05, pp. 272-278, 2005.
2.
J. Guo, S. Datta and M. Lundstrom, "Assessmentof silicon MOS and carbon nanotube FET performance limits using a generaltheory of ballistic transistors", Proc. IEDM02, pp. 711-715, 2002.
3.
S. J. Wind, J. Appenzeller and P. Avouris, "Lateral scaling in carbon-nanotube field-effecttransistors", Phys. Rev. Lett., vol. 91, no. 5, pp. 058301-1-058301-4, Aug. 2003.
4.
Y. Lin, J. Appenzeller, J. Knoch and P. Avouris, "High-performance carbon nanotube field-effecttransistor with tunable polarities", IEEE Trans. Nanotechnol., vol. 4, no. 9, Sep. 2005.
5.
A. Javey, "High performance n-type carbon nanotubefield-effect transistors with chemically doped contacts", Nano Lett., vol. 5, no. 2, pp. 345-348, 2005.
6.
J. Appenzeller, "Comparing carbon nanotube transistorstheideal choice: A novel tunneling device design", IEEE Trans. Electron Devices, vol. 52, no. 12, pp. 2568-2576, Dec. 2005.
7.
W. Hoenlein, "Carbon nanotubes for microelectronics:Status and future prospects", Mater. Sci. Eng. C23, pp. 663-669, 2003.
8.
P. Avouris, J. Appenzeller, R. Martel and S. J. Wind, "Carbon nanotube electronics", Proc. IEEE, vol. 91, no. 11, pp. 1772-1784, Nov. 2003.
9.
R. Saito, M. S. Dresselhaus and G. Dresselhaus, Physical Properties of Carbon Nanotubes, U.K., UK, London:Imperial College Press, 1998.
10.
A. Raychowdhury, S. Mukhopadhyay and K. Roy, "A circuit-compatible model of ballistic carbon nanotubefield-effect transistors", IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 10, pp. 1411-1420, Oct. 2004.
11.
S. Datta, Quantum TransportAtom to Transistor, U.K., Cambridge:Cambridge University Press, 2005.
12.
H. Cazin dHonincthun, S. Galdin-Retailleau, J. Se and P. Dollfus, "Electronphonon scattering and ballisticbehavior in semiconducting carbon nanotubes", Appl. Phys. Lett., vol. 87, pp. 172112, 2005.
13.
V. N. Popov and L. Henrard, "Comparative study of the optical properties of single-walledcarbon nanotubes within orthogonal and nonorthogonal tight-binding models", Phys. Rev. B, vol. 70, pp. 115;407-1-115407-12, 2004.
14.
C. Enz, F. Krummenacher and E. Vittoz, "An analytical MOS transistor model valid in all regionsof operation and dedicated to low-voltage and low-current applications", J. AICSP, pp. 83-114, 1995.
15.
C. Maneux, J. Goguet, S. Frgonse and T. Zimmer, "Analysis of CNTFET physicalcompact model", Proc. IEEE Int. Conf. Design Test Integr. Syst. (DTIS) Nano.Technol., pp. 40-45, 2006.
16.
F. Prgaldiny, C. Lallement and J.-B. Kammerer, "Design-oriented compact models for CNTFETS", Proc. IEEE Int. Conf. Design Test Integr. Syst. (DTIS) Nano.Technol., pp. 34-39, 2006.
17.
NANOHUB Online Simulations and More CNT Bands, Apr. 2006, [online] Available: http://www.nanohub.org.
18.
J. Knoch, S. Mantl and J. Appenzeller, "Comparison of transport propoerties in carbonnanotube field-effect transistors with Schottky contacts and doped source/draincontacts", Solid-State Electron., vol. 49, pp. 73-76, 2005.
19.
J. Guo, S. Datta and M. Lundstrom, "A numerical study of scaling issues forSchottky-barrier carbon nanotube transistors", IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 172-177, Feb. 2004.
20.
A. Hazeghi, T. Krishnamohan and H.-S. P. Wong, "Schottky-barrier carbon nanotubefield-effect transistor modeling", IEEE Trans. Electron Devices, vol. 54, no. 3, pp. 439-445, Mar. 2007.
21.
F. Prgaldiny, J.-B. Kammerer and C. Lallement, "Compact modeling and applicationsof CNTFETS for analog and digital circuit design", Proc. IEEE ICECS, pp. 1030-1033, 2006-Dec.-1013.
22.
A. Javey, "High-K dielectrics foradvanced carbon nanotube transistors and logic gates", Nature Mater., vol. 1, pp. 241-246, 2002.
23.
A. Bachtold, P. Hadley, T. Nakanishi and C. Dekker, "Logic circuits with carbonnanotube transistors", Sci, vol. 294, no. 5545, pp. 1317-1320, Nov. 2001.
24.
R. Martel, V. Derycke, J. Appenzeller, S. Wind and P. Avouris, "Carbon nanotube field-effect transistorsand logic circuits", Proc. 39th Design Autom. Conf., pp. 94-98, 2002-Jun.-1014.
25.
Z. Chen, J. Appenzeller, Y.-M. Lin, J. Sippel-Oakley, A. G. Rinzler, J. Tang, et al., "An integrated logic circuit assembled ona single carbon nanotube", Sci, vol. 311, no. 5768, pp. 1735-11735, Mar. 2006.
26.
A. Raychowdhury and K. Roy, "Carbon-nanotube-based voltage-mode multiple-valuedlogic design", IEEE Trans. Nanotechnol., vol. 4, no. 2, pp. 168-179, Mar. 2005.
27.
R. Sordan, K. Balasubramanian, M. Burghard and K. Kern, " Exclusive- or gatewith a single carbon nanotube ", Appl. Phys. Lett., vol. 88, pp. 053119, 2006.
28.
J.-M. Bethoux, H. Happy, G. Dambrine, V. Derycke, M. Goffman and J.-P. Bourgoin, " An 8-GHz \$f_{t}\$ carbonnanotube field-effect transistor for gigahertz range applications ", IEEE Electron Dev. Lett., vol. 27, no. 8, pp. 681-683, Aug. 2006.
29.
J. Guo, S. Hasan, A. Javey, G. Bosman and M. Lundstrom, "Assessment of high-frequency performance potential for carbonnanotube transistors", IEEE Trans. Nanotechnology, vol. 4, no. 6, pp. 715-721, Nov. 2005.

References

References is not available for this document.