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CNTFET Modeling and Reconfigurable Logic-Circuit Design | IEEE Journals & Magazine | IEEE Xplore

CNTFET Modeling and Reconfigurable Logic-Circuit Design


Abstract:

This paper examines aspects of design technology required to explore advanced logic-circuit design using carbon nanotube field-effect transistor (CNTFET) devices. An over...Show More

Abstract:

This paper examines aspects of design technology required to explore advanced logic-circuit design using carbon nanotube field-effect transistor (CNTFET) devices. An overview of current types of CNTFETs is given and highlights the salient characteristics of each. Compact modeling issues are addressed and new models are proposed implementing: 1) a physics-based calculation of energy conduction sub-band minima to allow a realistic analysis of the impact of CNT helicity and radius on the dc characteristics; 2) descriptions of ambipolar behavior in Schottky-barrier CNTFETs and ambivalence in double-gate CNTFETs (DG-CNTFETs). Using the available models, the influence of the parameters on the device characteristics were simulated and analyzed. The exploitation of properties specific to CNTFETs to build functions inaccessible to MOSFETs is also described, particularly with respect to the use of DG-CNTFETs in fine-grain reconfigurable logic.
Published in: IEEE Transactions on Circuits and Systems I: Regular Papers ( Volume: 54, Issue: 11, November 2007)
Page(s): 2365 - 2379
Date of Publication: 12 November 2007

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I. Introduction

The pursuit of moore's law, as predicted by the International Technology Roadmap for Semiconductors (ITRS) has pointed to significant future intrinsic device hurdles (such as leakage, interconnect, power, quantum effects) to the capability of realizing system architectures using CMOS transistors with the performance levels required by future applications. It is recognized that these limitations, as much fundamental as economic, require the semiconductor industry to explore the use of novel materials and devices able to complement or even replace the CMOS transistor in systems on chip within the next decade and before silicon based technology will reach its limits in 2020 when the channel length of MOSFET is below 10 nm.

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