Subhasish Mitra (S'97–M'00) received the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, in 2000.
Before joining Intel, he led the Stanford project on “Reliability Obtained by Adaptive Reconfiguration” sponsored by the Defense Advanced Research Projects Agency (DARPA) as part of the Adaptive Computing Systems program. He also consulted for several companies, including Agilent Technologies Laboratories. He is a Principal Engineer at Intel Corporation, Santa Clara, CA, where he is responsible for developing enabling technologies for robust system design—design for reliability, testability, and debug—in advanced technologies. He is also a Consulting Assistant Professor at the Electrical Engineering Department of Stanford University and the Associate Director of the Stanford Center for Reliable Computing. He has published more than 70 technical papers in leading conferences and journals, and invented design and test techniques that have seen widespread proliferation in the industry. His research interests include robust system design, very large scale integration (VLSI) design and test, computer-aided design (CAD), fault-tolerant computing, and computer architecture.
Dr. Mitra received recent major awards, including the IEEE Circuits and Systems Society 2005 Donald O. Pederson Award for the Best Paper published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and the 2004 Intel Achievement Award, Intel's highest corporate award, “for the development and deployment of a breakthrough test compression technology that achieved an order of magnitude improvement in scan test cost.” In addition, he received several Best Paper Award nominations, several recognition awards at Intel, several IEEE Computer Society Service Awards, and fellowships and awards for being the Best Student during his undergraduate studies. He served as the General Co-Chair of the 2005 IEEE System Effects of Logic Soft Errors (SELSE) workshop, 2005 CRC-IEEE Pacific Northwest Test Workshop, and is currently the Membership Chair of the IEEE Test Technology Technical Council. He has served on the organizing and program committees of several leading conferences such as the IEEE VLSI Test Symposium (VTS), the IEEE International Conference on Computer-Aided Design (ICCAD), Design Automation and Test in Europe (DATE), and the International Conference on Dependable Systems and Networks (DSN).
Subhasish Mitra (S'97–M'00) received the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, in 2000.
Before joining Intel, he led the Stanford project on “Reliability Obtained by Adaptive Reconfiguration” sponsored by the Defense Advanced Research Projects Agency (DARPA) as part of the Adaptive Computing Systems program. He also consulted for several companies, including Agilent Technologies Laboratories. He is a Principal Engineer at Intel Corporation, Santa Clara, CA, where he is responsible for developing enabling technologies for robust system design—design for reliability, testability, and debug—in advanced technologies. He is also a Consulting Assistant Professor at the Electrical Engineering Department of Stanford University and the Associate Director of the Stanford Center for Reliable Computing. He has published more than 70 technical papers in leading conferences and journals, and invented design and test techniques that have seen widespread proliferation in the industry. His research interests include robust system design, very large scale integration (VLSI) design and test, computer-aided design (CAD), fault-tolerant computing, and computer architecture.
Dr. Mitra received recent major awards, including the IEEE Circuits and Systems Society 2005 Donald O. Pederson Award for the Best Paper published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and the 2004 Intel Achievement Award, Intel's highest corporate award, “for the development and deployment of a breakthrough test compression technology that achieved an order of magnitude improvement in scan test cost.” In addition, he received several Best Paper Award nominations, several recognition awards at Intel, several IEEE Computer Society Service Awards, and fellowships and awards for being the Best Student during his undergraduate studies. He served as the General Co-Chair of the 2005 IEEE System Effects of Logic Soft Errors (SELSE) workshop, 2005 CRC-IEEE Pacific Northwest Test Workshop, and is currently the Membership Chair of the IEEE Test Technology Technical Council. He has served on the organizing and program committees of several leading conferences such as the IEEE VLSI Test Symposium (VTS), the IEEE International Conference on Computer-Aided Design (ICCAD), Design Automation and Test in Europe (DATE), and the International Conference on Dependable Systems and Networks (DSN).View more