A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration

This study presents a 15-b 40-MS/s switched-capacitor CMOS pipelined analog-to-digital converter (ADC). High resolution is achieved by using a correlation-based background calibration technique that can continuously monitor the transfer characteristics of the critical pipeline stages and correct the digital output codes accordingly. The calibration can correct errors associated with capacitor mismatches and finite opamp gains. The ADC was fabricated using a 0.25-/spl mu/m 1P5M CMOS technology. Operating at a 40-MS/s sampling rate, the ADC attains a maximum signal-to-noise-plus-distortion ratio of 73.5 dB and a maximum spurious-free-dynamic-range of 93.3 dB. The chip occupies an area of 3.8/spl times/3.6 mm/sup 2/, and the power consumption is 370 mW with a single 2.5-V supply.

I. Introduction

PIPELINED analog-to-digital converters (ADCs) are widely used in applications such as video imaging systems, broadband communication transceivers, and instrumentation. The subranging architecture offers a good tradeoff among power, sampling rate, and chip area for Nyquist-rate analog-to-digital (A/D) conversion.