Hiroshi Iwai (A'79–SM'93–F'97) was born in Tokyo, Japan, on April 25, 1949. He received the B.E. and Ph.D. degrees in electrical engineering from the University of Tokyo, Japan, in 1972 and 1992, respectively.
In 1973, he joined the Research and Development Center, Toshiba Corporation, Kawasaki, Japan, where he developed the first generation of Toshiba's NMOS LSI technology. From 1978 to 1980, he was also associated with NEC-Toshiba Information Systems, Inc., Kawasaki, Japan. From 1979 to 1989, he was with the Semiconductor Device Engineering Laboratory in the Semiconductor Group, Toshiba. In 1983 and 1984, he worked with Prof. R. W. Dutton at the Integrated Circuit Laboratory, Stanford University, Stanford, CA, as a Visiting Scholar, where he studied small-geometry effects of MOSFET capacitances. From 1989 to 1996, he was associated with the ULSI Research Laboratories in the Research and Development Center, Toshiba. From 1997 to March 1999, he was Chief Specialist of the Microelectronics Engineering Laboratories, Toshiba. Since April 1999, he has been a Professor with the Department of Advanced Applied Electronics, Interdisciplinary Graduate School of Science and Technology, Tokyo Institute of Technology, Yokohama, Japan. Since April 2001, he has also been a Member of the Frontier Collaborative Research Center, Tokyo Institute of Technology. Since joining Toshiba, he has developed several generations of high-density static RAMs, dynamic RAMs, and logic LSIs, including CMOS, bipolar, and Bi-CMOS devices. He has also been engaged in research on device physics, process technologies, and T-CAD related to small-geometry MOSFETs and high-speed bipolar transistors. His research area covers a wide range: isolation scaling analysis, deep ion-implanted channel doping techniques, on-chip capacitance measurement techniques, two-dimensional process and device simulation, small geometry MOSFET capacitance analysis, rapid thermal process, silicides techniques, interconnects techniques, nitrided oxide gate insulator techniques, p+polysilicon gate MOSFETs, polysilicon emitter techniques, BiCMOS process, hot carrier effects on small geometry MOS and bipolar transistors, bias temperature tests of MOSFETs, charge pumping measurement techniques, mechanical stress analysis of trench isolation, Ti-, Ni, Co-silicide techniques, 40-nm gate length MOSFETs and 1.5-nm-thick direct tunneling gate oxide MOSFETs, RF CMOS technologies, and so on. He has authored and coauthored more than 200 papers. He has served on many committees of conferences and as editor of many journals. His current research interests are downsizing of CMOS, high K gate insulator, ultrashallow junction, and RF silicon technologies for mobile telecommunication.
Dr. Iwai is an elected member of the IEEE EDS AdCom, an Editor of IEEE EDS Newsletter, a Guest Editor of IEEE TRANSACTIONS ON ELECTRON DEVICES, and an Editor of the Proceedings of ECS Symposium on ULSI Process Integration. He has been the Vice President of the IEEE EDS. His awards include Local Commendation for Invention from Japan Institute of Invention and Innovation (1990), Grand Prize of Nikkei BP Technology Awards (1994), IEEE EDS Paul Rappaport Award (1994), the IEICE ES Electronics Award (1998), and the IEEE EDS J. J. Ebers Award (2001). He is a member of the Electrochemical Society, the Japan Society of Applied Physics, the Institute of Electronics, Information, and Communication Engineers of Japan (IEICE), and the Institute of Electrical Engineers of Japan.
Hiroshi Iwai (A'79–SM'93–F'97) was born in Tokyo, Japan, on April 25, 1949. He received the B.E. and Ph.D. degrees in electrical engineering from the University of Tokyo, Japan, in 1972 and 1992, respectively.
In 1973, he joined the Research and Development Center, Toshiba Corporation, Kawasaki, Japan, where he developed the first generation of Toshiba's NMOS LSI technology. From 1978 to 1980, he was also associated with NEC-Toshiba Information Systems, Inc., Kawasaki, Japan. From 1979 to 1989, he was with the Semiconductor Device Engineering Laboratory in the Semiconductor Group, Toshiba. In 1983 and 1984, he worked with Prof. R. W. Dutton at the Integrated Circuit Laboratory, Stanford University, Stanford, CA, as a Visiting Scholar, where he studied small-geometry effects of MOSFET capacitances. From 1989 to 1996, he was associated with the ULSI Research Laboratories in the Research and Development Center, Toshiba. From 1997 to March 1999, he was Chief Specialist of the Microelectronics Engineering Laboratories, Toshiba. Since April 1999, he has been a Professor with the Department of Advanced Applied Electronics, Interdisciplinary Graduate School of Science and Technology, Tokyo Institute of Technology, Yokohama, Japan. Since April 2001, he has also been a Member of the Frontier Collaborative Research Center, Tokyo Institute of Technology. Since joining Toshiba, he has developed several generations of high-density static RAMs, dynamic RAMs, and logic LSIs, including CMOS, bipolar, and Bi-CMOS devices. He has also been engaged in research on device physics, process technologies, and T-CAD related to small-geometry MOSFETs and high-speed bipolar transistors. His research area covers a wide range: isolation scaling analysis, deep ion-implanted channel doping techniques, on-chip capacitance measurement techniques, two-dimensional process and device simulation, small geometry MOSFET capacitance analysis, rapid thermal process, silicides techniques, interconnects techniques, nitrided oxide gate insulator techniques, p+polysilicon gate MOSFETs, polysilicon emitter techniques, BiCMOS process, hot carrier effects on small geometry MOS and bipolar transistors, bias temperature tests of MOSFETs, charge pumping measurement techniques, mechanical stress analysis of trench isolation, Ti-, Ni, Co-silicide techniques, 40-nm gate length MOSFETs and 1.5-nm-thick direct tunneling gate oxide MOSFETs, RF CMOS technologies, and so on. He has authored and coauthored more than 200 papers. He has served on many committees of conferences and as editor of many journals. His current research interests are downsizing of CMOS, high K gate insulator, ultrashallow junction, and RF silicon technologies for mobile telecommunication.
Dr. Iwai is an elected member of the IEEE EDS AdCom, an Editor of IEEE EDS Newsletter, a Guest Editor of IEEE TRANSACTIONS ON ELECTRON DEVICES, and an Editor of the Proceedings of ECS Symposium on ULSI Process Integration. He has been the Vice President of the IEEE EDS. His awards include Local Commendation for Invention from Japan Institute of Invention and Innovation (1990), Grand Prize of Nikkei BP Technology Awards (1994), IEEE EDS Paul Rappaport Award (1994), the IEICE ES Electronics Award (1998), and the IEEE EDS J. J. Ebers Award (2001). He is a member of the Electrochemical Society, the Japan Society of Applied Physics, the Institute of Electronics, Information, and Communication Engineers of Japan (IEICE), and the Institute of Electrical Engineers of Japan.View more 
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