Comprehensive Capacitance–Voltage Simulation and Extraction Tool Including Quantum Effects for High-k on SixGe1−x and InxGa1−xAs: Part I—Model Description and Validation

High-mobility alternative channel materials to silicon are critical to the continued scaling of MOS devices. The analysis of capacitance–voltage (C–V) measurements on these new materials with high-k gate dielectrics is a critical technique to determine many important gate-stack parameters. While there are very useful C–V analysis tools available to the community, these tools are all limited in their applicability to alternative semiconductor channel MOS gate-stack analysis since they were developed for silicon. Here, we report on a new comprehensive C–V simulation and extraction tool, called CV Alternative Channel Extraction (ACE), that incorporates a wide range of semiconductors and dielectrics with the capability to implement customized gate stacks. Fermi–Dirac carrier statistics, nonparabolic bands, and quantum mechanical effects are all implemented with options to turn each of these off as the user desires. Interface state capacitance ( ${C}_{\mathsf {it}}$ ) is implemented using a common model for systems like Si and Ge. A more complex ${C}_{\mathsf {it}}$ model is also implemented for III–Vs that accurately captures frequency dispersion in accumulation that arises from tunneling. CV ACE enables extremely fast simulation and extraction and can accommodate measurements performed at variable temperatures and frequencies to allow for a more accurate extraction of interface state density ( ${D}_{\mathsf {it}}$ ).

I. Introduction

For current and future MOSFET technology, various alternative semiconductor channel materials are used or being considered to improve device performance, including Si-Ge [1], germanium [2]–[4], and III–V compound semiconductors [5]–[7]. These high-mobility channel materials, used in conjunction with high-k dielectrics [8] and metal gates may provide important advantages, leading to increased device density and performance while driving down the cost of manufacturing and energy consumption. However, characterizing experimentally fabricated gate stacks on these new channel materials is challenging.