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Don Disney - IEEE Xplore Author Profile

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Author details

Don Disney

Also published under: D. R. Disney, D. Disney, Donald Disney

Publications

34

Citations

864

Publications by Year

19922023

Co-Authors:

O. AktasA. A. AllermanM. A. AnnamalaiMuthukumaraswamy Annamalai ArasuA. M. Armstrong

Show All Co-Authors (108)

Don Disney

Also published under: D. R. Disney, D. Disney, Donald Disney

Affiliation

Infineon, Neubiberg, Germany

Publication Topics

Power Conversion,
Switching Frequency,
Ac Resistance,
Bond Wires,
Boost Converter,
Cobalt Oxide,
Conversion Efficiency,
Conversion Ratio,
Dc Resistance,
Dcdc Converter,
Eddy Current,
Eddy Current Loss

Biography

Don Disney received the B.S. degree in electrical engineering from Kettering University, Flint, MI, USA, in 1989, and the Ph.D. degree in electrical engineering from Stanford University, Palo Alto, CA, USA, in 1993. He has held senior engineering and management positions at Delco Electronics, Power Integrations, Advanced Analogic Technologies, Monolithic Power Systems, Avogy, GlobalFoundries, and Infineon. He is a Fellow of the IEEE(Based on document published on 13 September 2021).

Publications

34

Citations

864

Publications by Year

19922023

Co-Authors:

O. Aktas
A. A. Allerman
M. A. Annamalai
Muthukumaraswamy Annamalai Arasu
A. M. Armstrong

Show All Co-Authors (108)

Author's Published Works

Search History

Showing 1-25 of 154 results

Conferences (129)

Journals (25)

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R. Jammy(78)
P. D. Kirsch(64)
G. Bersuker(57)
P. Kirsch(37)
C. Hobbs(31)
SEMATECH, Austin, TX, USA(65)
SEMATECH, Albany, NY, USA(32)
SEMATECH, USA(19)
IBM, USA(10)
College of Nanoscale Science and Engineering, Albany, NY, USA(9)
IEEE Electron Device Letters(15)
Proceedings of Technical Program of 2012 VLSI Technology, System and Application(10)
2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)(7)
IEEE Transactions on Electron Devices(7)
Proceedings of 2010 International Symposium on VLSI Technology, System and Application(6)
IEEE(154)
Hsinchu, Taiwan(36)
San Francisco, CA, USA(17)
Kyoto, Japan(11)
Washington, DC, USA(10)
Honolulu, HI, USA(9)
Gate Stack(73)
Gate Dielectric(41)
Atomic Layer Deposition(34)
Metal Gate(28)
Carrier Mobility(27)

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Results

Improved 20nm device yield and gate dielectric integrity with optimized aluminum metal fill process

David Williams;Clint Bordelon;Sergei Drizlikh;Paul D. Kirsch;Kin-Sang Lam;Paul Coppala;Ian Guerassio;Nikhil Bharat Hira;Steven Trigno;Paul Nester;Ryan Paulsen;Anuj Patel;Jun-Han Kim;Jungmin Park;Taegyun Kim;Hee Sung Kang;Jinho Seo;Chulwan An;Sunjong Wang

2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)

Year: 2016 | Conference Paper |

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Titanium-aluminum (TiAl) alloys are the industry standard source for work function tuning of High-K nMOS transistors in the gate-last process architecture. When aluminum is used as a metal gate fill material, the TiAl alloy also serves as a diffusion barrier against excess aluminum migration into the work function metal and dielectric layers. However, the formation of the TiAl alloy by annealing t...Show More

Improved 20nm device yield and gate dielectric integrity with optimized aluminum metal fill process

David Williams;Clint Bordelon;Sergei Drizlikh;Paul D. Kirsch;Kin-Sang Lam;Paul Coppala;Ian Guerassio;Nikhil Bharat Hira;Steven Trigno;Paul Nester;Ryan Paulsen;Anuj Patel;Jun-Han Kim;Jungmin Park;Taegyun Kim;Hee Sung Kang;Jinho Seo;Chulwan An;Sunjong Wang

2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)

Year: 2016 | Conference Paper |

High-performance III–V devices for future logic applications

D.-H. Kim;T.-W. Kim;RH. Baek;P. D. Kirsch;W. Maszara;J. A. del Alamo;D. A. Antoniadis;M. Urteaga;B. Brar;HM. Kwon;C.-S. Shin;W.-K. Park;Y.-D. Cho;SH. Shin;DH. Ko;K.-S. Seo

2014 IEEE International Electron Devices Meeting

Year: 2014 | Conference Paper |

Cited by: Papers (19)

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High-mobility III-V transistors are poised to take the lead on future high performance logic operation. If this happens, indium-rich InxGa1-xAs is the most promising n-channel material. Indeed, remarkable progress has been made, including III-V gate-stacks with ALD-grown gate dielectrics. This paper reviews the evolution of high-performance III-V devices for future logic applications and discuss a...Show More

High-performance III–V devices for future logic applications

D.-H. Kim;T.-W. Kim;RH. Baek;P. D. Kirsch;W. Maszara;J. A. del Alamo;D. A. Antoniadis;M. Urteaga;B. Brar;HM. Kwon;C.-S. Shin;W.-K. Park;Y.-D. Cho;SH. Shin;DH. Ko;K.-S. Seo

2014 IEEE International Electron Devices Meeting

Year: 2014 | Conference Paper |

Sub-100 nm regrown S/D Gate-Last In0.7Ga0.3As QW MOSFETs with μn,eff > 5,500 cm2/V-s

C.-S. Shin;W.-K. Park;SH. Shin;YD. Cho;DH. Ko;T.-W. Kim;D.H. Koh;HM. Kwon;R. J. W. Hill;P. Kirsch;W. Maszara;D.-H. Kim

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers

Year: 2014 | Conference Paper |

Cited by: Papers (3)

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This paper reports on gate-last (GL) In0.7Ga0.3As QW MOSFETs with regrown S/D by MOCVD. Long-channel devices exhibit excellent electrostatics and carrier transport (SS=80mV/dec., DIBL=22mV/V, and μn,eff>5,500 cm2/V-s at 300k). Short-channel device with Lg = 40 nm also exhibit excellent electrostatic integrity of SS = 105 mV/dec., and DIBL = 150 mV/V, together with gm_max = 2 mS/μm at VDS = 0.5 V. ...Show More

Sub-100 nm regrown S/D Gate-Last In0.7Ga0.3As QW MOSFETs with μn,eff > 5,500 cm2/V-s

C.-S. Shin;W.-K. Park;SH. Shin;YD. Cho;DH. Ko;T.-W. Kim;D.H. Koh;HM. Kwon;R. J. W. Hill;P. Kirsch;W. Maszara;D.-H. Kim

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers

Year: 2014 | Conference Paper |

Electrostatics and performance benchmarking using all types of III–V multi-gate FinFETs for sub 7nm technology node logic application

R.-H. Baek;D.-H. Kim;T.-W. Kim;CS. Shin;WK. Park;T. Michalak;C. Borst;S. C. Song;Geoffrey Yeap;R. Hill;C. Hobbs;W. Maszara;P. Kirsch

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers

Year: 2014 | Conference Paper |

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In this paper, we conducted the sub 7nm technology benchmarking for logic application using performance comparison between III-V multi-gate(double, tri, gate-all-around) nMOSFET and Si nFinFET. The benchmarking was executed based on the physical parameters extracted from Virtual-Source(VS) modeling and well-calibrated TCAD simulation. Especially by quantitatively investigating fin width(Wfin) and ...Show More

Electrostatics and performance benchmarking using all types of III–V multi-gate FinFETs for sub 7nm technology node logic application

R.-H. Baek;D.-H. Kim;T.-W. Kim;CS. Shin;WK. Park;T. Michalak;C. Borst;S. C. Song;Geoffrey Yeap;R. Hill;C. Hobbs;W. Maszara;P. Kirsch

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers

Year: 2014 | Conference Paper |

Statistical demonstration of silicide-like uniform and ultra-low specific contact resistivity using a metal/high-k/Si stack in a sidewall contact test structure

K. Majumdar;R. Clark;T. Ngai;K. Tapily;S. Consiglio;E. Bersch;K. Matthews;E. Stinzianni;Y. Trickett;G. Nakamura;C. Wajda;G. Leusink;H. Chong;V. Kaushik;J. Woicik;C. Hobbs;P. Kirsch

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers

Year: 2014 | Conference Paper |

Cited by: Papers (5) | Patents (6)

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We demonstrate a 300mm wafer scale conformal contact process to achieve uniform ultra-low specific contact resistivity (ρc) for metal/high-k/n+Si (MIS) contacts. To achieve conformal contacts, we use a sidewall TLM (STLM) test structure that helps to minimize current crowding effect and variability. A systematic study is provided by varying doping density (ND), high-k material (LaOx, ZrOx and TiOx...Show More

Statistical demonstration of silicide-like uniform and ultra-low specific contact resistivity using a metal/high-k/Si stack in a sidewall contact test structure

K. Majumdar;R. Clark;T. Ngai;K. Tapily;S. Consiglio;E. Bersch;K. Matthews;E. Stinzianni;Y. Trickett;G. Nakamura;C. Wajda;G. Leusink;H. Chong;V. Kaushik;J. Woicik;C. Hobbs;P. Kirsch

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers

Year: 2014 | Conference Paper |

Physical understanding of graphene/metal hetero-contacts to enhance MoS2 field-effect transistors performance

Y. Du;L. Yang;J. Zhang;H. Liu;K. Majumdar;P. D. Kirsch;P. D. Ye

72nd Device Research Conference

Year: 2014 | Conference Paper |

Cited by: Papers (5)

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Semiconducting transition metal dichalcogenide (TMD) is a promising two-dimensional material with a potential for next-generation nanoelectronic applications [1-3]. One of the most studied TMD materials, MoS2, has become an emerging candidate in the field of flexible electronics. In this report, a monolayer graphene is sandwiched between the metal contact and the few-layer n-type MoS2 film to form...Show More

Physical understanding of graphene/metal hetero-contacts to enhance MoS2 field-effect transistors performance

Y. Du;L. Yang;J. Zhang;H. Liu;K. Majumdar;P. D. Kirsch;P. D. Ye

72nd Device Research Conference

Year: 2014 | Conference Paper |

Positive bias instability in gate-first and gate-last InGaAs channel n-MOSFETs

S. Deora;G. Bersuker;T. W. Kim;D. H. Kim;C. Hobbs;P. D. Kirsch;K. C. Sahoo;A. S. Oates

2014 IEEE International Reliability Physics Symposium

Year: 2014 | Conference Paper |

Cited by: Papers (8)

Instability under positive bias stress in the InGaAs channel n-MOSFETs with gate last Al2O3 and gate-first ZrO2/Al2O3 process flows is investigated. It is determined that the threshold voltage shift (ΔVT) during stress is primarily caused by a recoverable electron trapping at the pre-existing defects located predominantly in the Al2O3 interfacial layer (IL). Generation of new electron trapping def...Show More

Positive bias instability in gate-first and gate-last InGaAs channel n-MOSFETs

S. Deora;G. Bersuker;T. W. Kim;D. H. Kim;C. Hobbs;P. D. Kirsch;K. C. Sahoo;A. S. Oates

2014 IEEE International Reliability Physics Symposium

Year: 2014 | Conference Paper |

A Correlation Between Oxygen Vacancies and Reliability Characteristics in a Single Zirconium Oxide Metal-Insulator-Metal Capacitor

Hyuk-Min Kwon;Sung-Kyu Kwon;Kwang-Seok Jeong;Sung-Kwen Oh;Sun-Ho Oh;Woon-Il Choi;Tae-Woo Kim;Dae-Hyun Kim;Chang-Yong Kang;Byoung Hun Lee;Paul Kirsch;Hi-Deok Lee

IEEE Transactions on Electron Devices

Year: 2014 | Volume: 61, Issue: 8 | Journal Article |

Cited by: Papers (12) | Patents (2)

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A correlation between reliability characteristics and failure mechanisms for time-dependent dielectric breakdown for a single ZrO2 metal-insulator-metal capacitor has been studied. Frenkel-Poole emission was the dominant mechanism in the high electric field region. The extracted dynamic constant and trap energy level were 4.013 and 0.963 eV, respectively. The variation of α as a function of stress...Show More

A Correlation Between Oxygen Vacancies and Reliability Characteristics in a Single Zirconium Oxide Metal-Insulator-Metal Capacitor

Hyuk-Min Kwon;Sung-Kyu Kwon;Kwang-Seok Jeong;Sung-Kwen Oh;Sun-Ho Oh;Woon-Il Choi;Tae-Woo Kim;Dae-Hyun Kim;Chang-Yong Kang;Byoung Hun Lee;Paul Kirsch;Hi-Deok Lee

IEEE Transactions on Electron Devices

Year: 2014 | Volume: 61, Issue: 8 | Journal Article |

Mechanistic understanding of mobility degradation on gate-last ZrO2 with medium thermal budget annealing

T. Ngai;R. D. Clark;D. Veksler;K. Matthews;E. Bersch;D.C. Gilmer;G. Bersuker;R. Hill;C. Hobbs;K. Tapily;C. S. Wajda;S. Consiglio;T. Burroughs;S. Vivekanand;V. Kaushik;G. J. Leusink;P.D. Kirsch

Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

Year: 2014 | Conference Paper |

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In this paper, we provide a mechanistic understanding of mobility degradation of gate-last ZrO2 subjected to medium thermal budget annealing. We find that high-k post deposition anneal (PDA) even at modest temperatures can improve the interfacial layer (IL) and bulk oxide, but mobility suffers. The mechanism for this mobility degradation is the enhanced remote Coulomb scattering from nonstoichiome...Show More

Mechanistic understanding of mobility degradation on gate-last ZrO2 with medium thermal budget annealing

T. Ngai;R. D. Clark;D. Veksler;K. Matthews;E. Bersch;D.C. Gilmer;G. Bersuker;R. Hill;C. Hobbs;K. Tapily;C. S. Wajda;S. Consiglio;T. Burroughs;S. Vivekanand;V. Kaushik;G. J. Leusink;P.D. Kirsch

Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

Year: 2014 | Conference Paper |

Dielectric defects controlling instability in InGaAs n-MOSFETs with Al2O3/ZrO2 gate stack

S. Deora;G. Bersuker;W. -Y. Loh;K. Matthews;C. Hobbs;P. D. Kirsch

Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

Year: 2014 | Conference Paper |

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Instability under positive bias stress (DC and AC) in InGaAs channel nMOSFETs with a a 1nmAl2O3/5nmZrO2 gate stack is studied. It is determined that the threshold voltage shift (ΔVT) during stress is primarily caused by a recoverable electron trapping at pre-existing defects, which are located pre-dominantly in the Al2O3 interfacial layer (IL). Generation of new electron trapping defects is found ...Show More

Dielectric defects controlling instability in InGaAs n-MOSFETs with Al2O3/ZrO2 gate stack

S. Deora;G. Bersuker;W. -Y. Loh;K. Matthews;C. Hobbs;P. D. Kirsch

Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

Year: 2014 | Conference Paper |

Mapping Defect Density in MBE Grown ${\rm In}_{0.53}{\rm Ga}_{0.47}{\rm As}$ Epitaxial Layers on Si Substrate Using Esaki Diode Valley Characteristics

Kausik Majumdar;Paul Thomas;Wei-Yip Loh;Pui-Yee Hung;Ken Matthews;David Pawlik;Brian Romanczyk;Matthew Filmer;Abhinav Gaur;Ravi Droopad;Sean L. Rommel;Chris Hobbs;Paul D. Kirsch

IEEE Transactions on Electron Devices

Year: 2014 | Volume: 61, Issue: 6 | Journal Article |

Cited by: Papers (13)

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Growing good quality III–V epitaxial layers on Si substrate is of utmost importance to produce next generation high-performance devices in a cost effective way. In this paper, using physical analysis and electrical measurements of Esaki diodes, fabricated using molecular beam epitaxy grown

${\rm In}_{0.53}{\rm Ga}_{0.47}{\rm As}$ layers on Si substrate, we show that the valley current density is...Show More

Mapping Defect Density in MBE Grown ${\rm In}_{0.53}{\rm Ga}_{0.47}{\rm As}$ Epitaxial Layers on Si Substrate Using Esaki Diode Valley Characteristics

Kausik Majumdar;Paul Thomas;Wei-Yip Loh;Pui-Yee Hung;Ken Matthews;David Pawlik;Brian Romanczyk;Matthew Filmer;Abhinav Gaur;Ravi Droopad;Sean L. Rommel;Chris Hobbs;Paul D. Kirsch

IEEE Transactions on Electron Devices

Year: 2014 | Volume: 61, Issue: 6 | Journal Article |

${\rm MoS}_{2}$ Field-Effect Transistors With Graphene/Metal Heterocontacts

Yuchen Du;Lingming Yang;Jingyun Zhang;Han Liu;Kausik Majumdar;Paul D. Kirsch;Peide D. Ye

IEEE Electron Device Letters

Year: 2014 | Volume: 35, Issue: 5 | Journal Article |

Cited by: Papers (134)

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For the first time, n-type few-layer

${\rm MoS}_{2}$ field-effect transistors (FETs) with graphene/Ti as the heterocontacts have been fabricated, showing more than 160-mA/mm drain current at 1-

$\mu{\rm m}$ gate length with an ON-OFF current ratio of

$10^{7}$ . The enhanced electrical characteristic is confirmed in a nearly 2.1 times improvement in ON-resistance and a 3.3 times improvement in ...Show More

${\rm MoS}_{2}$ Field-Effect Transistors With Graphene/Metal Heterocontacts

Yuchen Du;Lingming Yang;Jingyun Zhang;Han Liu;Kausik Majumdar;Paul D. Kirsch;Peide D. Ye

IEEE Electron Device Letters

Year: 2014 | Volume: 35, Issue: 5 | Journal Article |

Benchmarking Transition Metal Dichalcogenide MOSFET in the Ultimate Physical Scaling Limit

Kausik Majumdar;Chris Hobbs;Paul D. Kirsch

IEEE Electron Device Letters

Year: 2014 | Volume: 35, Issue: 3 | Journal Article |

Cited by: Papers (48)

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In this letter, we propose a nonplanar transition metal dichalcogenide (TMD) channel field effect transistor and explore its ballistic performance in the ultimate scaling limit of sub-5 nm physical gate length (Lg) using self-consistent nonequilibrium Greens function framework. It is observed that electrostatic integrity remains intact even at such ultrashort Lg and physical scaling is eventually ...Show More

Benchmarking Transition Metal Dichalcogenide MOSFET in the Ultimate Physical Scaling Limit

Kausik Majumdar;Chris Hobbs;Paul D. Kirsch

IEEE Electron Device Letters

Year: 2014 | Volume: 35, Issue: 3 | Journal Article |

AC Variability and Endurance Measurement Technique for Resistive Switching Memories

S. Deora;G. Bersuker;K. Matthews;D. C. Gilmer;P. D. Kirsch

IEEE Transactions on Device and Materials Reliability

Year: 2014 | Volume: 14, Issue: 1 | Journal Article |

Cited by: Papers (7)

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Variability in resistive switching memory (RRAM) devices is studied by applying an AC measurement setup capable of efficiently collecting read current data in low and high resistance states (LRS and HRS, respectively) in each consecutive pulse SET/RESET cycle. It is found that HRS and LRS read current values follow the lognormal and normal distributions, respectively. Endurance test demonstrates t...Show More

AC Variability and Endurance Measurement Technique for Resistive Switching Memories

S. Deora;G. Bersuker;K. Matthews;D. C. Gilmer;P. D. Kirsch

IEEE Transactions on Device and Materials Reliability

Year: 2014 | Volume: 14, Issue: 1 | Journal Article |

Connecting RRAM performance to the properties of the hafnia-based dielectrics

Gennadi Bersuker;Brian Butcher;David Gilmer;Paul Kirsch;Luca Larcher;Andrea Padovani

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

Year: 2013 | Conference Paper |

Cited by: Papers (3)

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The connection between the resistive-RAM (RRAM) operational-mechanism, performance, and utilized-dielectric-properties is described. Specifically, the atomic-level description of bi-polar hafnia-based RRAM, which operations involve the repeatable rupture/recreation of a localized conductive path, reveals that its performance is determined by the outcome of the initial forming process; defining the...Show More

Connecting RRAM performance to the properties of the hafnia-based dielectrics

Gennadi Bersuker;Brian Butcher;David Gilmer;Paul Kirsch;Luca Larcher;Andrea Padovani

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

Year: 2013 | Conference Paper |

Connecting the physical and electrical properties of Hafnia-based RRAM

B. Butcher;G. Bersuker;D. C. Gilmer;L. Larcher;A. Padovani;L. Vandelli;R. Geer;P. D. Kirsch

2013 IEEE International Electron Devices Meeting

Year: 2013 | Conference Paper |

Cited by: Papers (22)

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Simulations of the dynamic physical processes involved in HfO2-based resistive-memory-operations are used to identify the dielectric structural properties responsible for device performance, while revealing that repeatable switching and higher HRS resistances are enabled by the oxide sub-stoichiometric composition. These simulations support a conductive-filament-formation physical model which is r...Show More

Connecting the physical and electrical properties of Hafnia-based RRAM

B. Butcher;G. Bersuker;D. C. Gilmer;L. Larcher;A. Padovani;L. Vandelli;R. Geer;P. D. Kirsch

2013 IEEE International Electron Devices Meeting

Year: 2013 | Conference Paper |

Sub-100 nm InGaAs quantum-well (QW) tri-gate MOSFETs with Al2O3/HfO2 (EOT < 1 nm) for low-power logic applications

T.-W. Kim;D.-H. Kim;D. H. Koh;H. M. Kwon;R. H. Baek;D. Veksler;C. Huffman;K. Matthews;S. Oktyabrsky;A. Greene;Y. Ohsawa;A. Ko;H. Nakajima;M. Takahashi;T. Nishizuka;H. Ohtake;S. K. Banerjee;S. H. Shin;D.-H. Ko;C. Kang;D. Gilmer;R. J. W. Hill;W. Maszara;C. Hobbs;P. D. Kirsch

2013 IEEE International Electron Devices Meeting

Year: 2013 | Conference Paper |

Cited by: Papers (13)

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This paper reports tri-gate sub-100 nm In0.53Ga0.47As QW MOSFETs with electrostatic immunity of S = 77 mV/dec., DIBL = 10 mV/V, together with excellent carrier transport of gm, max > 1.5 mS/μm, at VDS = 0.5 V. This result is the best balance of gm, max and S in any reported III-V MOSFETs. In addition, extracted compact model parameter including (μ0 = 760 cm2/V-s and peak vx0 = 1.6×107 cm/s) indica...Show More

Sub-100 nm InGaAs quantum-well (QW) tri-gate MOSFETs with Al2O3/HfO2 (EOT < 1 nm) for low-power logic applications

T.-W. Kim;D.-H. Kim;D. H. Koh;H. M. Kwon;R. H. Baek;D. Veksler;C. Huffman;K. Matthews;S. Oktyabrsky;A. Greene;Y. Ohsawa;A. Ko;H. Nakajima;M. Takahashi;T. Nishizuka;H. Ohtake;S. K. Banerjee;S. H. Shin;D.-H. Ko;C. Kang;D. Gilmer;R. J. W. Hill;W. Maszara;C. Hobbs;P. D. Kirsch

2013 IEEE International Electron Devices Meeting

Year: 2013 | Conference Paper |

VLSI processed InGaAs on Si MOSFETs with thermally stable, self-aligned Ni-InGaAs contacts achieving: Enhanced drive current and pathway towards a unified contact module

Rinus T. P. Lee;R. J. W. Hill;W.-Y. Loh;R.-H. Baek;S. Deora;K. Matthews;C. Huffman;K. Majumdar;T. Michalak;C. Borst;P.Y. Hung;C.-H. Chen;J.-H. Yum;T.-W. Kim;C. Y. Kang;Wei-E Wang;D.-H. Kim;C. Hobbs;P. D. Kirsch

2013 IEEE International Electron Devices Meeting

Year: 2013 | Conference Paper |

Cited by: Papers (4) | Patents (1)

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Parasitic resistance (Rpara) is a grand challenge to successfully hetero-integrate III-V channels onto Si for CMOS application. Here, we report the first statistical IDsat comparison for non-self-aligned and self-aligned contacts of In0.53Ga0.47As MOSFETs fabricated on large scale Si substrates with VLSI toolsets. We compare non-self-aligned Mo and self-aligned Ni-InGaAs contacts. Devices with sel...Show More

VLSI processed InGaAs on Si MOSFETs with thermally stable, self-aligned Ni-InGaAs contacts achieving: Enhanced drive current and pathway towards a unified contact module

Rinus T. P. Lee;R. J. W. Hill;W.-Y. Loh;R.-H. Baek;S. Deora;K. Matthews;C. Huffman;K. Majumdar;T. Michalak;C. Borst;P.Y. Hung;C.-H. Chen;J.-H. Yum;T.-W. Kim;C. Y. Kang;Wei-E Wang;D.-H. Kim;C. Hobbs;P. D. Kirsch

2013 IEEE International Electron Devices Meeting

Year: 2013 | Conference Paper |

Comprehensive layout and process optimization study of Si and III-V technology for sub-7nm node

C. Y. Kang;R-H. Baek;T-W Kim;D. Ko;D-H. Kim;T. Michalak;C. Borst;D. Veksler;G. Bersuker;R. Hill;C. Hobbs;P. D. Kirsch

2013 IEEE International Electron Devices Meeting

Year: 2013 | Conference Paper |

Cited by: Papers (1)

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In this work we present III-V device performance and its variability under various design and process parameters, as compared to Si devices, using MC simulation. III-V device compact/BSIM models are developed, including geometry-dependent parasitic RC. Compared to its Si counterpart, III-V devices exhibit superior performance in Ion, ring oscillator delay (tpd) and SRAM read time (tread). We calcu...Show More

Comprehensive layout and process optimization study of Si and III-V technology for sub-7nm node

C. Y. Kang;R-H. Baek;T-W Kim;D. Ko;D-H. Kim;T. Michalak;C. Borst;D. Veksler;G. Bersuker;R. Hill;C. Hobbs;P. D. Kirsch

2013 IEEE International Electron Devices Meeting

Year: 2013 | Conference Paper |

Positive Bias Instability and Recovery in InGaAs Channel nMOSFETs

S. Deora;G. Bersuker;W.-Y. Loh;D. Veksler;K. Matthews;T. W. Kim;R. T. P. Lee;R. J. W. Hill;D.-H. Kim;W.-E. Wang;C. Hobbs;P. D. Kirsch

IEEE Transactions on Device and Materials Reliability

Year: 2013 | Volume: 13, Issue: 4 | Journal Article |

Cited by: Papers (41)

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Instability of InGaAs channel nMOSFETs with the Al2O3/ ZrO2 gate stack under positive bias stress demonstrates recoverable and unrecoverable components, which can be tentatively assigned to the pre-existing and generated defects, respectively. The recoverable component is determined to be primarily associated with the defects in the Al2O3 interfacial layer (IL), the slow trapping at which is respo...Show More

Positive Bias Instability and Recovery in InGaAs Channel nMOSFETs

S. Deora;G. Bersuker;W.-Y. Loh;D. Veksler;K. Matthews;T. W. Kim;R. T. P. Lee;R. J. W. Hill;D.-H. Kim;W.-E. Wang;C. Hobbs;P. D. Kirsch

IEEE Transactions on Device and Materials Reliability

Year: 2013 | Volume: 13, Issue: 4 | Journal Article |

Threshold Voltage Shift Due to Charge Trapping in Dielectric-Gated AlGaN/GaN High Electron Mobility Transistors Examined in Au-Free Technology

Derek W. Johnson;Rinus T. P. Lee;Richard J. W. Hill;Man Hoi Wong;Gennadi Bersuker;Edwin L. Piner;Paul D. Kirsch;H. Rusty Harris

IEEE Transactions on Electron Devices

Year: 2013 | Volume: 60, Issue: 10 | Journal Article |

Cited by: Papers (55)

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We report on the investigation of the charge trapping characteristics of dielectric-gated AlGaN/GaN high electron mobility transistors (HEMTs) with atomic layer deposited HfO2 (Tetrakis-(ethylmethylamino)hafnium and H2O precursors). The impact of process development and tool contamination in an Au-free 200-mm silicon CMOS line is discussed. The interfacial GaOxNy layer is proposed to be the primar...Show More

Threshold Voltage Shift Due to Charge Trapping in Dielectric-Gated AlGaN/GaN High Electron Mobility Transistors Examined in Au-Free Technology

Derek W. Johnson;Rinus T. P. Lee;Richard J. W. Hill;Man Hoi Wong;Gennadi Bersuker;Edwin L. Piner;Paul D. Kirsch;H. Rusty Harris

IEEE Transactions on Electron Devices

Year: 2013 | Volume: 60, Issue: 10 | Journal Article |

Effects of layout and process parameters on device/circuit performance and variability for 10nm node FinFET technology

Chang Yong Kang;Changwoo Sohn;Rock-Hyun Baek;Chris Hobbs;Paul Kirsch;Raj Jammy

2013 Symposium on VLSI Technology

Year: 2013 | Conference Paper |

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We studied device and circuit performance and their variability for various design and process parameters using TCAD and an analytical RC model. At the 10nm technology node, σCpara and στpd became greater while σRpara and σIon diminish due to lower ρc. Lg, Hfin, Pf2f, and Pp2p were found to be key parameters for mitigating variability. Increasing Hfin provides a path for further performance and ar...Show More

Effects of layout and process parameters on device/circuit performance and variability for 10nm node FinFET technology

Chang Yong Kang;Changwoo Sohn;Rock-Hyun Baek;Chris Hobbs;Paul Kirsch;Raj Jammy

2013 Symposium on VLSI Technology

Year: 2013 | Conference Paper |

Optimal device architecture and hetero-integration scheme for III–V CMOS

Ze Yuan;Archana Kumar;Chien-Yu Chen;Aneesh Nainani;Peter Griffin;Albert Wang;Wei Wang;Man Hoi Wong;Ravi Droopad;Rocio Contreras-Guerrero;Paul Kirsch;Raj Jammy;James Plummer;Krishna C. Saraswat

2013 Symposium on VLSI Technology

Year: 2013 | Conference Paper |

Cited by: Patents (1)

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Low density-of-states (DOS) of carriers and higher dielectric constants in III–Vs warrants transistor architecture with better electrostatics than conventional bulk FinFETs [1]. Additionally, the integration of III–V FinFETs on 300mm silicon wafers is a key technological challenge due to the large lattice-mismatch between III–Vs and silicon [2]. This paper presents a statistical variability study ...Show More

Optimal device architecture and hetero-integration scheme for III–V CMOS

Ze Yuan;Archana Kumar;Chien-Yu Chen;Aneesh Nainani;Peter Griffin;Albert Wang;Wei Wang;Man Hoi Wong;Ravi Droopad;Rocio Contreras-Guerrero;Paul Kirsch;Raj Jammy;James Plummer;Krishna C. Saraswat

2013 Symposium on VLSI Technology

Year: 2013 | Conference Paper |

Development of a Semiempirical Compact Model for DC/AC Cell Operation of ${\rm HfO}_{\rm{x}}$ -Based ReRAMs

Jinwoo Noh;Minseok Jo;Chang Yong Kang;David Gilmer;Paul Kirsch;Jack C. Lee;Byoung Hun Lee

IEEE Electron Device Letters

Year: 2013 | Volume: 34, Issue: 9 | Journal Article |

Cited by: Papers (14)

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A semiempirical model that can simulate dc and pulse (ac) characteristics of filament-type HfOx-based resistance change random access memory (ReRAM) devices has been developed. Time-dependent device characteristics, because of the dynamic change in the filament size, were emulated using a modified ion migration model. This model describes the difference between SET and RESET operations using a cur...Show More

Development of a Semiempirical Compact Model for DC/AC Cell Operation of ${\rm HfO}_{\rm{x}}$ -Based ReRAMs

Jinwoo Noh;Minseok Jo;Chang Yong Kang;David Gilmer;Paul Kirsch;Jack C. Lee;Byoung Hun Lee

IEEE Electron Device Letters

Year: 2013 | Volume: 34, Issue: 9 | Journal Article |

STLM: A Sidewall TLM Structure for Accurate Extraction of Ultralow Specific Contact Resistivity

Kausik Majumdar;Saikumar Vivekanand;Craig Huffman;Ken Matthews;Tat Ngai;Chien Hao Chen;Rock Hyun Baek;Wei Yip Loh;Martin Rodgers;Harlan Stamper;Steven Gausepohl;Chang Yong Kang;Chris Hobbs;Paul D. Kirsch

IEEE Electron Device Letters

Year: 2013 | Volume: 34, Issue: 9 | Journal Article |

Cited by: Papers (16)

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We propose a very large scale integration compatible, modified transfer length method (TLM) structure, called sidewall TLM, to minimize the effect of spreading resistance and thus improving the resolution of the TLM method. This is achieved by allowing uniform current collection perpendicularly through the sidewall of the contact. We demonstrate statistically significant specific contact resistivi...Show More

STLM: A Sidewall TLM Structure for Accurate Extraction of Ultralow Specific Contact Resistivity

Kausik Majumdar;Saikumar Vivekanand;Craig Huffman;Ken Matthews;Tat Ngai;Chien Hao Chen;Rock Hyun Baek;Wei Yip Loh;Martin Rodgers;Harlan Stamper;Steven Gausepohl;Chang Yong Kang;Chris Hobbs;Paul D. Kirsch

IEEE Electron Device Letters

Year: 2013 | Volume: 34, Issue: 9 | Journal Article |

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