Y. Ohsawa

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Ultra low contact resistivity (< 1×10−8 Ω-cm2) to In0.53Ga0.47As fin sidewall (110)/(100) surfaces: Realized with a VLSI processed III–V fin TLM structure fabricated with III–V on Si substrates

Rinus T.P. Lee;Y. Ohsawa;C. Huffman;Y. Trickett;G. Nakamura;C. Hatem;K.V. Rao;F. Khaja;R. Lin;K. Matthews;K. Dunn;A. Jensen;T. Karpowicz;Peter F. Nielsen;E. Stinzianni;A. Cordes;P.Y. Hung;D.-H. Kim;R.J.W. Hill;W.-Y. Loh;C. Hobbs

2014 IEEE International Electron Devices Meeting

Year: 2014 | Conference Paper |

Cited by: Papers (3)

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We report a record low contact resistivity of sub-1.0×10-8 Ω.cm2 realized on n+ In0.53Ga0.47As fin sidewall surfaces. This is achieved with VLSI processed fin TLM structures on wafer scale III-V on Si substrates. A novel low-damage III-V fin etch was developed and fins down to 35 nm were fabricated. A surface treatment to smoothen the fin sidewall surfaces was proposed, which reduced sidewall surf...Show More

Ultra low contact resistivity (< 1×10−8 Ω-cm2) to In0.53Ga0.47As fin sidewall (110)/(100) surfaces: Realized with a VLSI processed III–V fin TLM structure fabricated with III–V on Si substrates

2014 IEEE International Electron Devices Meeting

Year: 2014 | Conference Paper |

Sub-100 nm InGaAs quantum-well (QW) tri-gate MOSFETs with Al2O3/HfO2 (EOT < 1 nm) for low-power logic applications

T.-W. Kim;D.-H. Kim;D. H. Koh;H. M. Kwon;R. H. Baek;D. Veksler;C. Huffman;K. Matthews;S. Oktyabrsky;A. Greene;Y. Ohsawa;A. Ko;H. Nakajima;M. Takahashi;T. Nishizuka;H. Ohtake;S. K. Banerjee;S. H. Shin;D.-H. Ko;C. Kang;D. Gilmer;R. J. W. Hill;W. Maszara;C. Hobbs;P. D. Kirsch

2013 IEEE International Electron Devices Meeting

Year: 2013 | Conference Paper |

Cited by: Papers (13)

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This paper reports tri-gate sub-100 nm In0.53Ga0.47As QW MOSFETs with electrostatic immunity of S = 77 mV/dec., DIBL = 10 mV/V, together with excellent carrier transport of gm, max > 1.5 mS/μm, at VDS = 0.5 V. This result is the best balance of gm, max and S in any reported III-V MOSFETs. In addition, extracted compact model parameter including (μ0 = 760 cm2/V-s and peak vx0 = 1.6×107 cm/s) indica...Show More

Sub-100 nm InGaAs quantum-well (QW) tri-gate MOSFETs with Al2O3/HfO2 (EOT < 1 nm) for low-power logic applications

2013 IEEE International Electron Devices Meeting

Year: 2013 | Conference Paper |

ETB-QW InAs MOSFET with scaled body for improved electrostatics

T.-W. Kim;D.-H Kim;D.-H. Koh;R. J. W. Hill;R. T. P. Lee;M. H Wong;T. Cunningham;J. A. del Alamo;S. K. Banerjee;S. Oktyabrsky;A. Greene;Y. Ohsawa;Y. Trickett;G Nakamura;Q. Li;K. M. Lau;C. Hobbs;P. D. Kirsch;R. Jammy

2012 International Electron Devices Meeting

Year: 2012 | Conference Paper |

Cited by: Papers (22) | Patents (2)

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This paper reports Extremely-Thin-Body (ETB) InAs quantum-well (QW) MOSFETs with improved electrostatics down to Lg = 50 nm (S =103 mV/dec, DIBL = 73 mV/V). These excellent metrics are achieved by using extremely thin body (1/3/1 nm InGaAs/InAs/InGaAs) quantum well structure with optimized layer design and a high mobility InAs channel. The ETB channel does not significantly degrade transport prope...Show More

ETB-QW InAs MOSFET with scaled body for improved electrostatics

2012 International Electron Devices Meeting

Year: 2012 | Conference Paper |

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Y. Ohsawa

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Ultra low contact resistivity (< 1×10−8 Ω-cm2) to In0.53Ga0.47As fin sidewall (110)/(100) surfaces: Realized with a VLSI processed III–V fin TLM structure fabricated with III–V on Si substrates

Ultra low contact resistivity (< 1×10−8 Ω-cm2) to In0.53Ga0.47As fin sidewall (110)/(100) surfaces: Realized with a VLSI processed III–V fin TLM structure fabricated with III–V on Si substrates

Sub-100 nm InGaAs quantum-well (QW) tri-gate MOSFETs with Al2O3/HfO2 (EOT < 1 nm) for low-power logic applications

Sub-100 nm InGaAs quantum-well (QW) tri-gate MOSFETs with Al2O3/HfO2 (EOT < 1 nm) for low-power logic applications

ETB-QW InAs MOSFET with scaled body for improved electrostatics

ETB-QW InAs MOSFET with scaled body for improved electrostatics

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